[U-Boot] [PATCH V3] mpc8572 additional end-point mode

[Ed Swarthout]

mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0.
Include host_agent == 0 decode for end-point determination.

This is not needed for the ds reference board since pcie3 will be a host
in order to connect to the uli chip.  Include it here as a reference for
other mpc8572 boards.

Signed-off-by: Ed Swarthout <Ed.Swarthout at freescale.com>
---

 board/freescale/mpc8572ds/mpc8572ds.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 70b548b..2a0d58a 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -244,7 +244,7 @@ void pci_init_board(void)
 		extern void fsl_pci_init(struct pci_controller *hose);
 		struct pci_controller *hose = &pcie2_hose;
 		int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
-			(host_agent == 6);
+			(host_agent == 6) || (host_agent == 0);
 		int pcie_configured  = io_sel & 4;
 
 		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -300,7 +300,7 @@ void pci_init_board(void)
 		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 		extern void fsl_pci_init(struct pci_controller *hose);
 		struct pci_controller *hose = &pcie1_hose;
-		int pcie_ep = (host_agent == 1) || (host_agent == 4) ||
+		int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
 			(host_agent == 5);
 		int pcie_configured  = io_sel & 6;
 
-- 
1.5.6.5