[U-Boot] [PATCH] Fix USB init sequence for the lwmon5 board.

[Matthias Fuchs]

On Thursday 09 October 2008 13:25, sascha.laue at liebherr.com wrote:
> From: Sascha Laue <sascha.laue at liebherr.com>
> 
> Signed-off-by: Sascha Laue <sascha.laue at liebherr.com>
> ---
>  board/lwmon5/lwmon5.c |   44 +++++++++++++++++++++++++++++++++++++++-----
>  1 files changed, 39 insertions(+), 5 deletions(-)
> 
> diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
> index 8975bfd..5e310f4 100644
> --- a/board/lwmon5/lwmon5.c
> +++ b/board/lwmon5/lwmon5.c
> @@ -145,7 +145,7 @@ int misc_init_r(void)
>  	u32 reg;
>  	unsigned long usb2d0cr = 0;
>  	unsigned long usb2phy0cr, usb2h0cr = 0;
> -	unsigned long sdr0_pfc1;
> +	unsigned long sdr0_pfc1, sdr0_srst;
>  
>  	/*
>  	 * FLASH stuff...
> @@ -207,6 +207,15 @@ int misc_init_r(void)
>  	/*
>  	 * USB suff...
>  	 */
> +
> +	/* Reset USB peripherie */
> +	mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D );
> +        mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI \
> +		| SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 \
> +		| SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40 );
> +
I think these mtsdrs are not needed. These bits are all set after CPU reset.
So setting them again makes no sense.

But this reset sequence is full of magic at all. So I could imagine that it's needed :-)

Matthias

> +	udelay(100);	
> +
>  	/* SDR Setting */
>  	mfsdr(SDR0_PFC1, sdr0_pfc1);
>  	mfsdr(SDR0_USB0, usb2d0cr);
> @@ -234,13 +243,38 @@ int misc_init_r(void)
>  	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
>  	mtsdr(SDR0_USB2H0CR, usb2h0cr);
>  
> -	/*
> -	 * Clear resets
> -	 */
> +	/* the 440EPx controllers need this sequence to initiate the EHCI */
> +	
> +	/* deassert reset to USBPHY */
> +	mfsdr(SDR0_SRST1, sdr0_srst);
> +	sdr0_srst &= ~SDR0_SRST1_USB20PHY;
> +	mtsdr(SDR0_SRST1, sdr0_srst);
> +
>  	udelay (1000);
> -	mtsdr(SDR0_SRST1, 0x00000000);
> +
> +	/* deassert reset to HOST*/
> +	mfsdr(SDR0_SRST1, sdr0_srst);
> +	sdr0_srst &= ~( SDR0_SRST0_USB2H );
> +	mtsdr(SDR0_SRST1, sdr0_srst);
> +
> +	udelay(4000);
> +
> +	/* deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1, OPB2PLB40 cores */
> +	mfsdr(SDR0_SRST1, sdr0_srst);
> +	sdr0_srst &= ~( SDR0_SRST1_OPBA1 	| \ 
> +			SDR0_SRST1_P4OPB0       | \
> +			SDR0_SRST1_OPBA2        | \
> +			SDR0_SRST1_PLB42OPB1    | \
> +			SDR0_SRST1_OPB2PLB40);
> +	mtsdr(SDR0_SRST1, sdr0_srst);
> +
>  	udelay (1000);
> +	
> +	/* deassert all other resets */
>  	mtsdr(SDR0_SRST0, 0x00000000);
> +	mtsdr(SDR0_SRST1, 0x00000000);
> +
> +	udelay(1000);
>  
>  	printf("USB:   Host(int phy) Device(ext phy)\n");
>  

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