[U-Boot] [PATCH 1/2] Fix the incorrect DDR clk freq reporting on 8536DS

[Andy Fleming]

On Sat, Sep 27, 2008 at 1:40 AM, Jason Jin <Jason.jin at freescale.com> wrote:
> On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
> The display is still sync mode DDR freq. This patch try to fix
> this. The display DDR freq is now the actual freq in both
> sync and async mode.
>
> Signed-off-by: Jason Jin <Jason.jin at freescale.com>

Applied, thanks