[U-Boot] [PATCH 01/13 v4] ARM: OMAP3: Add pin mux, clock and cpu headers
Jean-Christophe PLAGNIOL-VILLARD
plagnioj at jcrosoft.com
Sun Oct 19 21:07:01 CEST 2008
On 21:25 Fri 17 Oct , dirk.behme at googlemail.com wrote:
> Subject: [PATCH 01/13 v4] ARM: OMAP3: Add pin mux, clock and cpu headers
>
> From: Dirk Behme <dirk.behme at gmail.com>
>
> Add pin mux, clock and cpu header files for OMAP3.
>
> Signed-off-by: Dirk Behme <dirk.behme at gmail.com>
>
> ---
>
> Changes in version v3:
>
> - Replace space by tabs in headers as proposed by Jean-Christophe PLAGNIOL-VILLARD
>
> include/asm-arm/arch-omap3/bits.h | 48 +++
> include/asm-arm/arch-omap3/clocks.h | 62 ++++
> include/asm-arm/arch-omap3/clocks_omap3.h | 101 +++++++
> include/asm-arm/arch-omap3/cpu.h | 249 ++++++++++++++++++
> include/asm-arm/arch-omap3/mux.h | 407 ++++++++++++++++++++++++++++++
> 5 files changed, 867 insertions(+)
> +#define CONTROL_PADCONF_DSS_DATA13 0x00F6
> +#define CONTROL_PADCONF_DSS_DATA14 0x00F8
> +#define CONTROL_PADCONF_DSS_DATA15 0x00FA
> +#define CONTROL_PADCONF_DSS_DATA16 0x00FC
> +#define CONTROL_PADCONF_DSS_DATA17 0x00FE
> +#define CONTROL_PADCONF_DSS_DATA18 0x0100
> +#define CONTROL_PADCONF_DSS_DATA19 0x0102
> +#define CONTROL_PADCONF_DSS_DATA20 0x0104
> +#define CONTROL_PADCONF_DSS_DATA21 0x0106
> +#define CONTROL_PADCONF_DSS_DATA22 0x0108
> +#define CONTROL_PADCONF_DSS_DATA23 0x010A
> +/*CAMERA*/
> +#define CONTROL_PADCONF_CAM_HS 0x010C
^
white space please remove
> +#define CONTROL_PADCONF_CAM_VS 0x010E
^
white space please remove
> +#define CONTROL_PADCONF_CAM_XCLKA 0x0110
> +#define CONTROL_PADCONF_CAM_PCLK 0x0112
> +#define CONTROL_PADCONF_CAM_FLD 0x0114
> +#define CONTROL_PADCONF_CAM_D0 0x0116
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D1 0x0118
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D2 0x011A
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D3 0x011C
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D4 0x011E
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D5 0x0120
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D6 0x0122
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D7 0x0124
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D8 0x0126
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D9 0x0128
^
white space please remove
> +#define CONTROL_PADCONF_CAM_D10 0x012A
> +#define CONTROL_PADCONF_CAM_D11 0x012C
> +#define CONTROL_PADCONF_CAM_XCLKB 0x012E
> +#define CONTROL_PADCONF_CAM_WEN 0x0130
> +#define CONTROL_PADCONF_CAM_STROBE 0x0132
> +#define CONTROL_PADCONF_CSI2_DX0 0x0134
> +#define CONTROL_PADCONF_CSI2_DY0 0x0136
> +#define CONTROL_PADCONF_CSI2_DX1 0x0138
> +#define CONTROL_PADCONF_CSI2_DY1 0x013A
> +/*Audio Interface */
> +#define CONTROL_PADCONF_McBSP2_FSX 0x013C
please use upercase for macro
> +#define CONTROL_PADCONF_McBSP2_CLKX 0x013E
ditto
> +#define CONTROL_PADCONF_McBSP2_DR 0x0140
ditto
> +#define CONTROL_PADCONF_McBSP2_DX 0x0142
ditto
> +#define CONTROL_PADCONF_MMC1_CLK 0x0144
> +#define CONTROL_PADCONF_MMC1_CMD 0x0146
> +#define CONTROL_PADCONF_MMC1_DAT0 0x0148
> +#define CONTROL_PADCONF_MMC1_DAT1 0x014A
> +#define CONTROL_PADCONF_MMC1_DAT2 0x014C
> +#define CONTROL_PADCONF_MMC1_DAT3 0x014E
> +#define CONTROL_PADCONF_MMC1_DAT4 0x0150
> +#define CONTROL_PADCONF_MMC1_DAT5 0x0152
> +#define CONTROL_PADCONF_MMC1_DAT6 0x0154
> +#define CONTROL_PADCONF_MMC1_DAT7 0x0156
> +/*Wireless LAN */
> +#define CONTROL_PADCONF_MMC2_CLK 0x0158
> +#define CONTROL_PADCONF_MMC2_CMD 0x015A
> +#define CONTROL_PADCONF_MMC2_DAT0 0x015C
> +#define CONTROL_PADCONF_MMC2_DAT1 0x015E
> +#define CONTROL_PADCONF_MMC2_DAT2 0x0160
> +#define CONTROL_PADCONF_MMC2_DAT3 0x0162
> +#define CONTROL_PADCONF_MMC2_DAT4 0x0164
> +#define CONTROL_PADCONF_MMC2_DAT5 0x0166
> +#define CONTROL_PADCONF_MMC2_DAT6 0x0168
> +#define CONTROL_PADCONF_MMC2_DAT7 0x016A
> +/*Bluetooth*/
> +#define CONTROL_PADCONF_McBSP3_DX 0x016C
ditto
> +#define CONTROL_PADCONF_McBSP3_DR 0x016E
ditto
> +#define CONTROL_PADCONF_McBSP3_CLKX 0x0170
ditto
> +#define CONTROL_PADCONF_McBSP3_FSX 0x0172
ditto and other
> +#define CONTROL_PADCONF_UART2_CTS 0x0174
> +#define CONTROL_PADCONF_UART2_RTS 0x0176
> +#define CONTROL_PADCONF_UART2_TX 0x0178
> +#define CONTROL_PADCONF_UART2_RX 0x017A
> +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16
> +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
> +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
> +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
> +#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C
> +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E
> +#define CONTROL_PADCONF_JTAG_TMS 0x0A20
> +#define CONTROL_PADCONF_JTAG_TDI 0x0A22
> +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24
> +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26
> +#define CONTROL_PADCONF_ETK_CLK 0x0A28
> +#define CONTROL_PADCONF_ETK_CTL 0x0A2A
> +#define CONTROL_PADCONF_ETK_D0 0x0A2C
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D1 0x0A2E
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D2 0x0A30
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D3 0x0A32
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D4 0x0A34
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D5 0x0A36
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D6 0x0A38
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D7 0x0A3A
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D8 0x0A3C
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D9 0x0A3E
^
white space please remove
> +#define CONTROL_PADCONF_ETK_D10 0x0A40
> +#define CONTROL_PADCONF_ETK_D11 0x0A42
> +#define CONTROL_PADCONF_ETK_D12 0x0A44
> +#define CONTROL_PADCONF_ETK_D13 0x0A46
> +
> +#endif
> Index: u-boot-arm/include/asm-arm/arch-omap3/bits.h
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/include/asm-arm/arch-omap3/bits.h
> @@ -0,0 +1,48 @@
> +/* bits.h
> + * Copyright (c) 2004 Texas Instruments
> + *
> + * This package is free software; you can redistribute it and/or
> + * modify it under the terms of the license found in the file
> + * named COPYING that should have accompanied this file.
> + *
> + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
> + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
> + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
> + */
> +#ifndef __bits_h
> +#define __bits_h 1
> +
> +#define BIT0 (1<<0)
plase add space to be more easy to read
#define BIT0 (1 << 0)
> +#define BIT1 (1<<1)
> +#define BIT2 (1<<2)
> +#define BIT3 (1<<3)
> +#define BIT4 (1<<4)
> +#define BIT5 (1<<5)
> +#define BIT6 (1<<6)
> +#define BIT7 (1<<7)
> +#define BIT8 (1<<8)
> +#define BIT9 (1<<9)
> +#endif
> Index: u-boot-arm/include/asm-arm/arch-omap3/clocks.h
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/include/asm-arm/arch-omap3/clocks.h
> @@ -0,0 +1,62 @@
> +/*
> + * (C) Copyright 2006-2008
> + * Texas Instruments, <www.ti.com>
> + * Richard Woodruff <r-woodruff2 at ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
^
white space please remove
> +#ifndef _CLOCKS_H_
> +#define _CLOCKS_H_
> +
> +#define LDELAY 12000000
> +
> +#define S12M 12000000
> +#define S13M 13000000
> +#define S19_2M 19200000
> +#define S24M 24000000
> +#define S26M 26000000
> +#define S38_4M 38400000
> +
> + unsigned int fsel;
> + unsigned int m2;
> +} dpll_param;
> +
> +/* Following functions are exported from lowlevel_init.S */
> +extern dpll_param *get_mpu_dpll_param(void);
> +extern dpll_param *get_iva_dpll_param(void);
> +extern dpll_param *get_core_dpll_param(void);
> +extern dpll_param *get_per_dpll_param(void);
> +
> +extern void *_end_vect, *_start;
> +
> +#endif
> Index: u-boot-arm/include/asm-arm/arch-omap3/clocks_omap3.h
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/include/asm-arm/arch-omap3/clocks_omap3.h
> @@ -0,0 +1,101 @@
> +/*
> + * (C) Copyright 2006-2008
> + * Texas Instruments, <www.ti.com>
> + * Richard Woodruff <r-woodruff2 at ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
^
white space please remove
> +#ifndef _CLOCKS_OMAP3_H_
> +#define _CLOCKS_OMAP3_H_
> +
> +#define PLL_STOP 1 /* PER & IVA */
> +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
> +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
> +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
> +
> +/* The following configurations are OPP and SysClk value independant
> + * and hence are defined here. All the other DPLL related values are
> + * tabulated in lowlevel_init.S.
> + */
> +
> +/* CORE DPLL */
> +#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
> +#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
> +#define CORE_FUSB_DIV 2 /* 41.5MHz: */
> +#define CORE_L4_DIV 2 /* 83MHz : L4 */
^
white space please remove
> +#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
> +#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
^
white space please remove
> +#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
> +
> +/* PER DPLL */
> +#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
> +#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
> +#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
> +#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
> +
> +#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50))
please use only one syle 0xaa or 0xAA
> +
> +#define M_12 0xA6
> +#define N_12 0x05
> +#define FSEL_12 0x07
> +#define M2_12 0x01 /* M3 of 2 */
> +
> +
> +#endif /* endif _CLOCKS_OMAP3_H_ */
> Index: u-boot-arm/include/asm-arm/arch-omap3/cpu.h
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/include/asm-arm/arch-omap3/cpu.h
> @@ -0,0 +1,249 @@
> +/*
> + * (C) Copyright 2006-2008
> + * Texas Instruments, <www.ti.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef _CPU_H
> +#define _CPU_H
> +
> +/* Register offsets of common modules */
> +/* Control */
> +#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0)
> +#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C)
> +#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C)
> +#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534)
> +
> +/* Tap Information */
> +#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204)
please add space
#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE + 0x204)
> +#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208)
ditto
> +
> +/* device type */
> +#define DEVICE_MASK (BIT8|BIT9|BIT10)
ditto
> +#define TST_DEVICE 0x0
> +#define EMU_DEVICE 0x1
> +#define HS_DEVICE 0x2
> +#define GP_DEVICE 0x3
> +
> +/* GPMC CS3/cs4/cs6 not avaliable */
> +#define GPMC_BASE (OMAP34XX_GPMC_BASE)
> +#define GPMC_SYSCONFIG (OMAP34XX_GPMC_BASE+0x10)
ditto
> +#define GPMC_IRQSTATUS (OMAP34XX_GPMC_BASE+0x18)
ditto
> +#define GPMC_IRQENABLE (OMAP34XX_GPMC_BASE+0x1C)
ditto
> +#define GPMC_TIMEOUT_CONTROL (OMAP34XX_GPMC_BASE+0x40)
ditto
> +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50)
ditto
> +#define GPMC_STATUS (OMAP34XX_GPMC_BASE+0x54)
ditto
> +
> +#define GPMC_CONFIG_CS0 (OMAP34XX_GPMC_BASE+0x60)
ditto
> +#define GPMC_CONFIG_WIDTH (0x30)
> +
> +#define GPMC_CONFIG1 (0x00)
> +#define GPMC_CONFIG2 (0x04)
> +#define GPMC_CONFIG3 (0x08)
> +#define GPMC_CONFIG4 (0x0C)
> +#define GPMC_CONFIG5 (0x10)
> +#define GPMC_CONFIG6 (0x14)
> +#define GPMC_CONFIG7 (0x18)
> +#define GPMC_NAND_CMD (0x1C)
> +#define GPMC_NAND_ADR (0x20)
> +#define GPMC_NAND_DAT (0x24)
> +
> +/* SMS */
> +#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10)
ditto
> +#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE+0x48)
ditto
> +#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE+0xD0)
ditto
> +#define BURSTCOMPLETE_GROUP7 BIT31
> +
> +/* SDRC */
> +#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE+0x10)
ditto
> +#define SDRC_STATUS (OMAP34XX_SDRC_BASE+0x14)
ditto
> +#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE+0x40)
ditto
> +#define SDRC_SHARING (OMAP34XX_SDRC_BASE+0x44)
ditto
> +#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE+0x60)
ditto
> +#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE+0x64)
ditto
> +#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE+0x68)
ditto
> +#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE+0x6C)
ditto
> +#define DLLPHASE BIT1
> +#define LOADDLL BIT2
> +#define DLL_DELAY_MASK 0xFF00
> +#define DLL_NO_FILTER_MASK (BIT8|BIT9)
ditto
> +
> +#define SDRC_POWER (OMAP34XX_SDRC_BASE+0x70)
ditto
> +#define WAKEUPPROC BIT26
> +
> +#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE+0x80)
ditto
> +#define SDRC_MR_0 (OMAP34XX_SDRC_BASE+0x84)
ditto
> +#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE+0x9C)
ditto
> +#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE+0xA0)
ditto
> +#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0xC4)
ditto
> +#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xC8)
ditto
> +#define SDRC_RFR_CTRL (OMAP34XX_SDRC_BASE+0xA4)
ditto
> +#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8)
ditto
> +#define OMAP34XX_SDRC_CS0 0x80000000
> +#define OMAP34XX_SDRC_CS1 0xA0000000
> +#define CMD_NOP 0x0
> +#define CMD_PRECHARGE 0x1
> +#define CMD_AUTOREFRESH 0x2
> +#define CMD_ENTR_PWRDOWN 0x3
> +#define CMD_EXIT_PWRDOWN 0x4
> +#define CMD_ENTR_SRFRSH 0x5
> +#define CMD_CKE_HIGH 0x6
> +#define CMD_CKE_LOW 0x7
> +#define SOFTRESET BIT1
> +#define SMART_IDLE (0x2 << 3)
> +#define REF_ON_IDLE (0x1 << 6)
> +
> +/* timer regs offsets (32 bit regs) */
> +#define TIDR 0x0 /* r */
> +#define TIOCP_CFG 0x10 /* rw */
> +#define TISTAT 0x14 /* r */
> +#define TISR 0x18 /* rw */
> +#define TIER 0x1C /* rw */
> +#define TWER 0x20 /* rw */
> +#define TCLR 0x24 /* rw */
> +#define TCRR 0x28 /* rw */
> +#define TLDR 0x2C /* rw */
> +#define TTGR 0x30 /* rw */
> +#define TWPS 0x34 /* r */
> +#define TMAR 0x38 /* rw */
> +#define TCAR1 0x3c /* r */
> +#define TSICR 0x40 /* rw */
> +#define TCAR2 0x44 /* r */
> + /* enable sys_clk NO-prescale /1 */
> +#define GPT_EN ((0<<2)|BIT1|BIT0)
ditto
> +
> +/* Watchdog */
> +#define WWPS 0x34 /* r */
> +#define WSPR 0x48 /* rw */
> +#define WD_UNLOCK1 0xAAAA
> +#define WD_UNLOCK2 0x5555
> +
Best Regards,
J.
More information about the U-Boot
mailing list