[U-Boot] amcc kilauea odd crashes

[Adam Graham]

> 
> Hi Wolfgang,
> 
> On Thursday 23 October 2008, Wolfgang Denk wrote:
> > > > Should we not backout the autocalib patches that cause 
> the problem 
> > > > until a stable working solution is found?
> > >
> > > Not sure. My hope is that AMCC find a solution quickly. 
> They should 
> > > receive the failing board this week.

We have not received this board yet and hope to try out our unreleased patches on your Kilauea board.  (That being said, it looks like Markus' Kilauea configuration can also be used to test the unreleased patches - CPU 400MHz, PLB 200MHz.)


> > >
> > > And they already did send a "fix" (more a workaround) for 
> this problem:
> > >
> > > [PATCH v2] ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz
> > >
> > > which you rejected. So I suggest to wait for a few days.
> >
> > Well, that was one full month ago, and nothing happened since.1s
> 
> That's not correct. One patch got checked in which definitely 
> made the situation better:
> 
> f8a00dea841d5d75de1f8e8107e90ee1beeddf5f
> 
>     ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
>     
>     After changing SDRAM_CLKTR phase value rerun the memory preload
>     initialization sequence (INITPLR) to reset and relock the memory
>     DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
>     adjustment effects the phase relationship of the internal, to the
>     PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.
>     
>     Signed-off-by: Adam Graham <agraham at amcc.com>
>     Signed-off-by: Victor Gallardo <vgallardo at amcc.com>
>     Signed-off-by: Stefan Roese <sr at denx.de>
> 
> Unfortunately it didn't fix all problems. AMCC already 
> provided another patch for testing purposes. Not to the list 
> but to me (and you) directly. Please find it attached again. 
> Would be great if Markus could test it on the failing Kilauea.

Stefan, thank you for send the test patch to Markus.

Markus, if you like to test out this patch and send us (AMCC) the results, that would be appreciated.  To get more DDR autocalibration information, you can set the U-Boot environment variable "autocalib" to "loop".  This will display all the passing and non-passing write-read-compare memory windows as well as the final result that was chosen.

=> setenv autocalib loop
=> saveenv
=> reset

To remove the "autocalib" verbosity, unset this "autocalib" environment variable.

Thanks,
Adam Graham
AMCC