[U-Boot] amcc kilauea odd crashes

Adam Graham agraham at amcc.com
Fri Oct 24 03:54:42 CEST 2008


 

> Subject: Re: [U-Boot] amcc kilauea odd crashes
> 
> On Thursday 23 October 2008, Markus Klotzbücher wrote:
> > > Unfortunately it didn't fix all problems. AMCC already provided 
> > > another patch for testing purposes. Not to the list but 
> to me (and you) directly.
> > > Please find it attached again. Would be great if Markus 
> could test 
> > > it on the failing Kilauea.
> >
> > I tested it and it's still failing. I dare say the patch 
> makes things 
> > worse. After about 20 hard resets the board didn't reach the u-boot 
> > console a single time.
> >
> > :-(
> 

Markus, yes, thank you for your testing and debug efforts.

> Too bad. Thanks for testing though.
> 
> Adam & Victor, any ideas? If you don't see a "quick" 
> solution, please provide a temporary fix for this problem.
> 

Markus, the only quick solution that we have for immediate application is to disable the DDR autocalibration and therefore run with the original Kilauea SDRAM static values.  This will require you to recompile U-Boot and download it onto your board.  

To disable the DDR autocalibration code, in the include/configs/kilauea.h file, undef the "CONFIG_PPC4xx_DDR_AUTOCALIBRATION" definition and recompile U-Boot.

Once we receive Stefan's Kilauea board we can debug his DDR autocalibration issue, which probably is a similar issue to what you are seeing on your board.  We will keep you in the loop.

As an aside I grabbed the top of git tree and tried it on all my Kilauea boards, including the latest board which supports (CPU=600MHz, PLB=200MHz) clocking and I can not get DDR autocalibration to fail.  I also successfully tried the PPC405EX chip built-in bootstraps of (CPU=333MHz PLB=166MHz, CPU=400MHz PLB=200MHz) and the bootstrap EEPROM strapping of (CPU=533MHz PLB=177MHz).

Thanks,
Adam


> Thanks.
> 
> Best regards,
> Stefan
> 
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