[U-Boot] [PATCH] 85xx: Fix the incorrect register used for DDR erratum1

[Andy Fleming]

On Oct 23, 2008, at 08:18, Dave Liu wrote:

> The 8572 DDR erratum1:
> DDR controller may enter an illegal state when operating
> in 32-bit bus mode with 4-beat bursts.
>
> Description:
> When operating with a 32-bit bus, it is recommended that
> DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
> This forces the DDR controller to use 4-beat bursts when
> communicating to the DRAMs. However, an issue exists that
> could lead to data corruption when the DDR controller is
> in 32-bit bus mode while using 4-beat bursts.
>
> Projected Impact:
> If the DDR controller is operating in 32-bit bus mode with
> 4-beat bursts, then the controller may enter into a bad state.
> All subsequent reads from memory is corrupted.
> Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
> Therefore, this erratum does not affect DDR3 mode.
>
> Work Arounds:
> To work around this issue, software must set DEBUG_1[31] in
> DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
> and CCSRBAR offset + 0x6f00 for DDR_2).
>
> Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
> as condition, but it should be DDR_SDRAM_CFG register.
>
> Signed-off-by: Dave Liu <daveliu at freescale.com>

Applied, thanks

Andy