[U-Boot] [PATCH][for 1.3.5] 85xx: Ensure timebase is zero on secondary cores

[Kumar Gala]

On Sep 5, 2008, at 11:10 AM, Scott Wood wrote:

> On Fri, Sep 05, 2008 at 08:45:11AM -0500, Kumar Gala wrote:
>> diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
>> index 75676b5..2ae6057 100644
>> --- a/cpu/mpc85xx/release.S
>> +++ b/cpu/mpc85xx/release.S
>> @@ -37,6 +37,11 @@ __secondary_start_page:
>> 	li	r3,0x201
>> 	mtspr	SPRN_BUCSR,r3
>>
>> +	/* Ensure TB is 0 */
>> +	li	r3,0
>> +	mttbu	r3
>> +	mttbl	r3
>
> If it's possible that TBL is a small negative number out of reset,  
> then
> we should write TBL before TBU to avoid a rollover race.

Time base is disabled at this point, so it should be moving AT ALL.

- k