[U-Boot] Data cache on MPC8248 board

[Rodrigo Vilar]

Hi all,

I have enabled cache on a MPC8248 board using Block Address Translation. RAM
is cache enabled, everything else cache inhibited.
Apparently cache is enabled fine, however system hangs using tftp command
(in the middle of the transaction) or on external interrupt handling when I
set up a timer from a standalone application. Please note that if I define
DBAT0 cache inhibited, both tftp and the standalone program work fine.

Any help or advice is appreciated.

Find below the code I have used to replace dcache_enable in
cpu/mpc8260/start.S, you will notice I am very novice with MPC assembler.

#define  BL_16Mb 0x000000FC
#define  BL_32Mb 0x000001FC
#define  BL_64Mb 0x000003FC
#define  BL_128Mb 0x000007FC
#define  BL_256Mb 0x00001FFC
#define  Valid_Supervisor 0x00000002
#define  Valid_User       0x00000001

#define  Cache_Inhibited   0x00000020
#define  Guarded           0x00000008

#define  Read_Write       0x00000002

#define CTR 9
 .globl dcache_enable
dcache_enable:
// Step 1: Disable_Cache
addis r3, r0, 0
ori r3, r3, 0xC000
sync
isync
mfspr r11, HID0
isync
andc r4, r11, r3
ori r12, r11, 0x0C00
sync
isync
mtspr HID0, r12
mtspr HID0, r4
isync
 // Step 2: Disable_Memory_Management
sync
li r12, 0x0030
mfmsr r11
andc r11, r11, r12
mtmsr r11
isync

// Step 3: Clear_Memory_Map
lis r3, 0
lis r4, 0
mtspr IBAT0U, r3
mtspr IBAT0L, r4
isync
mtspr DBAT0U, r3
mtspr DBAT0L, r4
isync
mtspr IBAT1U, r3
mtspr IBAT1L, r4
isync
mtspr DBAT1U, r3
mtspr DBAT1L, r4
isync
mtspr IBAT2U, r3
mtspr IBAT2L, r4
isync
mtspr DBAT2U, r3
mtspr DBAT2L, r4
isync
mtspr IBAT3U, r3
mtspr IBAT3L, r4
isync
mtspr DBAT3U, r3
mtspr DBAT3L, r4
isync

// Step 4: Set_Memory_Map
lis r3, 0x0000
ori r3, r3, BL_128Mb + Valid_Supervisor + Valid_User
lis r4, 0x0000
ori r4, r4, Read_Write
mtspr IBAT0U, r3
mtspr IBAT0L, r4
isync

lis r3, 0x0000
ori r3, r3, BL_128Mb + Valid_Supervisor + Valid_User
lis r4, 0x0000
ori r4, r4, Read_Write + Guarded
mtspr DBAT0U, r3
mtspr DBAT0L, r4
isync

lis r3, 0x5000
ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User
lis r4, 0x5000
ori r4, r4, Read_Write + Guarded + Cache_Inhibited
mtspr DBAT1U, r3
mtspr DBAT1L, r4
isync

lis r3, 0xF000
ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User
lis r4, 0xF000
ori r4, r4, Read_Write + Guarded + Cache_Inhibited
mtspr DBAT2U, r3
mtspr DBAT3L, r4
isync

// Step 5: Enable_Memory_Management

li r11, 64
mtspr CTR, r11
 isync
tlbie 0x00
sync
isync
tlbie 0x01
sync
isync
tlbie 0x02
sync
isync
tlbie 0x03
sync
isync
tlbie 0x04
sync
isync
tlbie 0x05
sync
isync
tlbie 0x06
sync
isync
tlbie 0x07
sync
isync
tlbie 0x08
sync
isync
tlbie 0x09
sync
isync
tlbie 0x0A
sync
isync
tlbie 0x0B
sync
isync
tlbie 0x0C
sync
isync
tlbie 0x0D
sync
isync
tlbie 0x0E
sync
isync
tlbie 0x0F
sync
isync
tlbie 0x10
sync
isync
tlbie 0x11
sync
isync
tlbie 0x12
sync
isync
tlbie 0x13
sync
isync
tlbie 0x14
sync
isync
tlbie 0x15
sync
isync
tlbie 0x16
sync
isync
tlbie 0x17
sync
isync
tlbie 0x18
sync
isync
tlbie 0x19
sync
isync
tlbie 0x1A
sync
isync
tlbie 0x1B
sync
isync
tlbie 0x1C
sync
isync
tlbie 0x1D
sync
isync
tlbie 0x1E
sync
isync
tlbie 0x1F
sync
 mfmsr r11
ori r11, r11, 0x0030
mtmsr r11
isync
 // Step 6: Enable_Cache
mfspr r11, HID0
ori r12, r11, 0xCC00
ori r11, r11, 0xC000
sync
isync
mtspr HID0, r12
mtspr HID0, r11
isync

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