[U-Boot] Data cache on MPC8248 board

[Rodrigo Vilar]

Snooping is enabled on all the devices we handle. However it is not enabled
on u-boot's serial console.
We have managed to get dcache running making the following changes, I
provide the answer should anyone be interested:

1) We have created a new function bat_enable, that defines the address
translation for our board
.globl bat_enable
bat_enable:
//  Set_Memory_Map
lis r3, 0x0000
ori r3, r3, BL_128Mb + Valid_Supervisor + Valid_User
lis r4, 0x0000
ori r4, r4, Read_Write
mtspr IBAT0U, r3
mtspr IBAT0L, r4
isync

lis r3, 0x0000
ori r3, r3, BL_128Kb + Valid_Supervisor + Valid_User
lis r4, 0x0000
ori r4, r4, Read_Write + Guarded + Cache_Inhibited
mtspr DBAT0U, r3
mtspr DBAT0L, r4
isync

   lis r3, 0x0002
ori r3, r3, BL_128Mb + Valid_Supervisor + Valid_User
lis r4, 0x0002
ori r4, r4, Read_Write + Guarded
mtspr DBAT1U, r3
mtspr DBAT1L, r4
isync

lis r3, 0x5000
ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User
lis r4, 0x5000
ori r4, r4, Read_Write + Guarded + Cache_Inhibited
mtspr DBAT2U, r3
mtspr DBAT2L, r4
isync

lis r3, 0xF000
ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User
lis r4, 0xF000
ori r4, r4, Read_Write + Guarded + Cache_Inhibited
mtspr DBAT3U, r3
mtspr DBAT3L, r4
isync

li r3, 32
mtctr r3
li r3, 0
1: tlbie r3
addi r3, r3, 0x1000
bdnz 1b
SYNC

/* Enable address translations */
mfmsr r3
ori r3, r3, 0x0030
mtmsr r3
isync

blr

2) We call this function in lib_ppc/board.c within function board_init_r
before serial_initialise. Probably this is not the best location, any advice
would be appreciated.

3) We had to modify include/ppc_asm.tmpl macro STD_EXCEPTION

rlwimi r20,r23,0,25,25; \  changed to rlwimi r20,r23,0,25,27; \

in order to keep the data translation bits in MSR after the interrupt. The
instruction above is also used on CRITICAL_EXCEPTION, any advice on wether
we should change it or not would also be appreciated.

4) We had to modify lib_ppc/interrupts.c function enable_interrupts adding
asm("sync"); so as not to get "Bogus External Interrupt IRQ 0" after
enabling data cache.

void enable_interrupts (void)
{
asm ("sync");
set_msr (get_msr () | MSR_EE);
}


Thanks,

Rodrigo

2008/9/11 Scott Wood <scottwood at freescale.com>

> On Wed, Sep 10, 2008 at 10:51:50AM +0200, Rodrigo Vilar wrote:
> > I have enabled cache on a MPC8248 board using Block Address Translation.
> RAM
> > is cache enabled, everything else cache inhibited.
> > Apparently cache is enabled fine, however system hangs using tftp command
> > (in the middle of the transaction) or on external interrupt handling when
> I
> > set up a timer from a standalone application. Please note that if I
> define
> > DBAT0 cache inhibited, both tftp and the standalone program work fine.
>
> Do you have snooping enabled on all of the DMA devices you're using?
>
> > lis r3, 0xF000
> > ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User
> > lis r4, 0xF000
> > ori r4, r4, Read_Write + Guarded + Cache_Inhibited
> > mtspr DBAT2U, r3
> > mtspr DBAT3L, r4
> > isync
>
> s/DBAT3L/DBAT2L/, presumably.
>
> -Scott
>