[U-Boot] [PATCH v2] OMAP3: Fix timer handling to 1ms and CONFIG_SYS_HZ to 1000.

Ladislav Michl ladis at linux-mips.org
Thu Apr 2 12:48:25 CEST 2009


From: Manikandan Pillai <mani.pillai at ti.com>
Signed-off-by: Dirk Behme <dirk.behme at googlemail.com>
Signed-off-by: Manikandan Pillai <mani.pillai at ti.com>
Signed-off-by: Ladislav Michl <ladis at linux-mips.org>
---
Changes from Dirk's patch which is replaced by this [2]:

* Fix conflicts after commit 81472d893fa565c9d300928a40e504a689bde131

Changes from Mani's original patch which is replaced by this [1]:

* Don't remove overflow handling in get_timer_masked()
* Update omap3_zoom1.h, too.
* Clean up timer related comments and macros in config files
* Don't touch reset_timer_masked()
* Switch divider clock divider from 256 to 8 to be able to get 1000Hz
* Remove unused udelay_masked()
* Minor clean up of get_tbclk()

[1] http://lists.denx.de/pipermail/u-boot/2009-March/049012.html
[2] http://lists.denx.de/pipermail/u-boot/2009-March/049146.html
---
 cpu/arm_cortexa8/omap3/interrupts.c |   50 +++++++++++-----------------------
 include/configs/omap3_beagle.h      |    9 +++---
 include/configs/omap3_evm.h         |    9 +++---
 include/configs/omap3_overo.h       |   12 ++++----
 include/configs/omap3_pandora.h     |   11 ++++---
 include/configs/omap3_zoom1.h       |   11 ++++---
 6 files changed, 44 insertions(+), 58 deletions(-)

diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/interrupts.c
index 5d9c4e3..c75bc8b 100644
--- a/cpu/arm_cortexa8/omap3/interrupts.c
+++ b/cpu/arm_cortexa8/omap3/interrupts.c
@@ -169,7 +169,16 @@ static ulong timestamp;
 static ulong lastinc;
 static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
 
-/* nothing really to do with interrupts, just starts up a counter. */
+/*
+ * Nothing really to do with interrupts, just starts up a counter.
+ * We run the counter with 13MHz, divided by 8, resulting in timer
+ * frequency of 1.625MHz. With 32bit counter register, counter
+ * overflows in ~44min
+ */
+
+/* 13MHz / 8 = 1.625MHz */
+#define TIMER_CLOCK	(V_SCLK / (2 << CONFIG_SYS_PTV))
+
 int interrupt_init(void)
 {
 	/* start the counter ticking up, reload value on overflow */
@@ -232,50 +241,25 @@ void udelay(unsigned long usec)
 void reset_timer_masked(void)
 {
 	/* reset time, capture current incrementer value time */
-	lastinc = readl(&timer_base->tcrr);
+	lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
 	timestamp = 0;		/* start "advancing" time stamp from 0 */
 }
 
 ulong get_timer_masked(void)
 {
-	ulong now = readl(&timer_base->tcrr); /* current tick value */
+	/* current tick value */
+	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
 
 	if (now >= lastinc)	/* normal mode (non roll) */
 		/* move stamp fordward with absoulte diff ticks */
 		timestamp += (now - lastinc);
 	else	/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
+		timestamp += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ))
+				- lastinc) + now;
 	lastinc = now;
 	return timestamp;
 }
 
-/* waits specified delay value and resets timestamp */
-void udelay_masked(unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	/* if "big" number, spread normalization to seconds */
-	if (usec >= 1000) {
-		/* start to normalize for usec to ticks per sec */
-		tmo = usec / 1000;
-		/* find number of "ticks" to wait to achieve target */
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;	/* finish normalize. */
-	} else {		/* else small number, */
-				/* don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000 * 1000);
-	}
-	endtime = get_timer_masked() + tmo;
-
-	do {
-		ulong now = get_timer_masked();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
 /*
  * This function is derived from PowerPC code (read timebase as long long).
  * On ARM it just returns the timer value.
@@ -291,7 +275,5 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk(void)
 {
-	ulong tbclk;
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
+	return CONFIG_SYS_HZ;
 }
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 7db1eb7..88a57d3 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -223,12 +223,13 @@
 							/* load address */
 
 /*
- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
-#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Stack sizes
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 2f532d5..d36e689 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -216,12 +216,13 @@
 								/* address */
 
 /*
- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
  */
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
-#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
-#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Stack sizes
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 0c32100..ec8529e 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -208,14 +208,14 @@
 
 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
 								/* address */
-
 /*
- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
  */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
-#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Stack sizes
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index fb4e50d..f44d071 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -212,12 +212,13 @@
 								/* address */
 
 /*
- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
  */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
-#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Stack sizes
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 883234a..bfe40b3 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -220,12 +220,13 @@
 							/* load address */
 
 /*
- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
  */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
-#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Stack sizes
-- 
1.5.3.8



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