[U-Boot] [PATCH 2/9] MPC85xx: Change QE RISC ALLOCATION to support 4 RISCs

[Haiying Wang]

Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.

Signed-off-by: Haiying Wang <Haiying.Wang at freescale.com>
---
 drivers/qe/qe.c            |    3 ---
 drivers/qe/qe.h            |   15 ++++++++++-----
 drivers/qe/uec.c           |   30 ++++++++++++++++++++++++++++++
 drivers/qe/uec.h           |    4 ++--
 include/asm-ppc/immap_qe.h |    8 ++++++++
 5 files changed, 50 insertions(+), 10 deletions(-)

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index ea5a14b..a8e9399 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -257,9 +257,6 @@ int qe_set_mii_clk_src(int ucc_num)
 	return 0;
 }
 
-/* The maximum number of RISCs we support */
-#define MAX_QE_RISC     2
-
 /* Firmware information stored here for qe_get_firmware_info() */
 static struct qe_firmware_info qe_firmware_info;
 
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index d78edba..1eb0a74 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -46,11 +46,16 @@ typedef struct qe_snum {
 
 /* QE RISC allocation
 */
-typedef enum qe_risc_allocation {
-	QE_RISC_ALLOCATION_RISC1		= 1,  /* RISC 1 */
-	QE_RISC_ALLOCATION_RISC2		= 2,  /* RISC 2 */
-	QE_RISC_ALLOCATION_RISC1_AND_RISC2	= 3   /* RISC 1 or RISC 2 */
-} qe_risc_allocation_e;
+#define	QE_RISC_ALLOCATION_RISC1	0x1  /* RISC 1 */
+#define	QE_RISC_ALLOCATION_RISC2	0x2  /* RISC 2 */
+#define	QE_RISC_ALLOCATION_RISC3	0x4  /* RISC 3 */
+#define	QE_RISC_ALLOCATION_RISC4	0x8  /* RISC 4 */
+#define	QE_RISC_ALLOCATION_RISC1_AND_RISC2 	(QE_RISC_ALLOCATION_RISC1 | \
+						 QE_RISC_ALLOCATION_RISC2)
+#define	QE_RISC_ALLOCATION_FOUR_RISCS	(QE_RISC_ALLOCATION_RISC1 | \
+					 QE_RISC_ALLOCATION_RISC2 | \
+					 QE_RISC_ALLOCATION_RISC3 | \
+					 QE_RISC_ALLOCATION_RISC4)
 
 /* QE CECR commands for UCC fast.
 */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2..119e3d3 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.riscTx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.riscRx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.riscTx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.riscRx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.riscTx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.riscRx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.riscTx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.riscRx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC4_PHY_ADDR,
@@ -138,8 +158,13 @@ static uec_info_t eth5_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.riscTx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.riscRx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC5_PHY_ADDR,
@@ -161,8 +186,13 @@ static uec_info_t eth6_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.riscTx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.riscRx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC6_PHY_ADDR,
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 0b64499..411f0d2 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -654,8 +654,8 @@ typedef struct uec_info {
 	ucc_fast_info_t			uf_info;
 	uec_num_of_threads_e		num_threads_tx;
 	uec_num_of_threads_e		num_threads_rx;
-	qe_risc_allocation_e		riscTx;
-	qe_risc_allocation_e		riscRx;
+	unsigned int			riscTx;
+	unsigned int			riscRx;
 	u16				rx_bd_ring_len;
 	u16				tx_bd_ring_len;
 	u8				phy_address;
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 66a4735..9530b29 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -602,4 +602,12 @@ extern qe_map_t *qe_immr;
 #define QE_MURAM_SIZE		0x4000UL
 #endif
 
+#if defined(CONFIG_MPC8323)
+#define MAX_QE_RISC     1
+#elif defined(CONFIG_MPC8569)
+#define MAX_QE_RISC     4
+#else
+#define MAX_QE_RISC	2
+#endif
+
 #endif				/* __IMMAP_QE_H__ */
-- 
1.6.0.2