[U-Boot] [PATCH] NAND: DaVinci: Adding 4 BIT ECC support

[Wolfgang Denk]

Dear Scott Wood,

In message <20090818151213.GB26119 at b07421-ec1.am.freescale.net> you wrote:
> On Tue, Aug 18, 2009 at 08:56:03AM -0500, Paulraj, Sandeep wrote:
> > > > +	case NAND_ECC_READSYN:
> > > > +		val = emif_regs->NAND4BITECC1;
> > > 
> > > Use I/O accessors.
> > I could not understand this one. It is done similarly nand_davinci_enable_hwecc which is used for 1 BIT ECC.
> > NANDFCR is a control register and we have to write the appropriate valvue to it.
> > We similarly write to other register that are part of the IP in other sections of this driver.
> 
> Well, the comment applies to the rest of the driver too.  I won't NACK
> because of it, but it's something to consider in the future.

Well, I will NAK it, then.

We should really write clean code these days.


Best regards,

Wolfgang Denk

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