[U-Boot] [PATCH] NAND: DaVinci: Update 4 bit ECC correction

[Scott Wood]

Paulraj, Sandeep wrote:
>> Is it possible that there could be a race, whereby the hardware finishes
>> before you read NANDFSR for the first time, and thus you never see it be
>> greater than 3?
> 
> There are other check conditions after this check condition in the driver.
> If we never see the concetned value greater than 3, that actually
> means that ECC calculation has finished or not required at all
> because there were no errors

And this patch will respond to that by hanging, waiting for a value 
greater than 3.

-Scott