[U-Boot] [PATCH] Add new Elpida memory configuration for ads5121

Wolfgang Denk wd at denx.de
Sat Feb 21 23:42:24 CET 2009


Dear Martha Marx,

In message <12351364353259-git-send-email-mmarx at silicontkx.com> you wrote:
> Rev 3 and earlier stay with Micron memory settings.  Rev 4 boards
> manufactured before Nov-08 #1180 also will use Micron settings.  More
> recent boards use Elpida settings.
> 
> Signed-off-by: Martha Marx <mmarx at silicontkx.com>
> ---
>  board/ads5121/ads5121.c   |  114 +++++++++++++++++++++++++++++++++-----------
>  include/configs/ads5121.h |   41 ++++++++++------
>  2 files changed, 110 insertions(+), 45 deletions(-)

Can you please swap the order of your patches, i. e. first perform the
global CONFIG_SYS_ rename, and then apply the Elpida support patch?

> diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
> index 6c40e94..1983492 100644
> --- a/board/ads5121/ads5121.c
> +++ b/board/ads5121/ads5121.c
> @@ -124,9 +124,15 @@ phys_size_t initdram (int board_type)
>   * fixed sdram init -- the board doesn't use memory modules that have serial presence
>   * detect or similar mechanism for discovery of the DRAM settings
>   */
> +
>  long int fixed_sdram (void)
>  {
> +	u32 use_micron = 0;
>  	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> +	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
> +	char *mac, *end, macaddr[6];
> +	u32 brddate, macchk;
> +
>  	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
>  	u32 msize_log2 = __ilog2 (msize);
>  	u32 i;
> @@ -174,41 +180,91 @@ long int fixed_sdram (void)
>  	im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
>  	im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
>  
> +	if (brd_rev >= 0x0400 && (mac = getenv("ethaddr"))) {
> +		for (i=0; i<6; i++) {
> +		 	macaddr[i] = mac ? 
> +				simple_strtoul (mac, &end, 16) : 0;
> +			if (mac)
> +				mac = (*end) ? end+1 : end;
> +		}

Please rebase your patch(es) against the "next" branch, so you can use 
eth_getenv_enetaddr() instead of manually paring the MAC address.

> +		brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
> +		macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
> +		debug("brddate = %d\n\t",brddate);
> +	/* Boards made before Nov-08 #1180 use Micron memory; 001e59 is the STx vendor # */

Wrong indentation; line too long.

> +		if (macchk == 0x001e59 && brddate <= 8111180) 
> +			use_micron = 1;
> +	} else if (brd_rev < 0x400) {
> +		use_micron = 1;
> +	}
> +
> +	debug("Using %s Memory settings\n\t", use_micron ? "Micron" : "Elpida");
> +
>  	/* Initialize MDDRC */
> -	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
> -	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
> -	im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
> -	im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
> +	if (use_micron) {
> +		im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_MICRON;
> +		im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
> +		im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_MICRON;
> +		im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_MICRON;
> +	} else {
> +		im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA;
> +		im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
> +		im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA;
> +		im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA;
> +	}
>  
>  	/* Initialize DDR */
>  	for (i = 0; i < 10; i++)
> -		im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
> -
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
> -	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
> -
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
> +
> +	im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL;
> +	im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
> +	im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
> +	im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
> +	im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
> +	im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
> +
> +	if (use_micron) {
> +	/* Micron init sequence */

Wrong indentation.

> +		im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL;
> +		im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
> +		im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
> +		udelay(200);
> +	} else {
> +	/* Elpida init sequence - works for Micron too but runs slower */

Wrong indentation.

> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_RES_DLL;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
> +		im->mddrc.ddr_command = CONFIG_SYS_ELPIDA_INIT_DEV_OP;
> +		udelay(200);
> +	}

Empty line, please.

> +	im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_DEFAULT;
> +	im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_EXIT;
> +	im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;

Empty line, please.

> +	for (i = 0; i < 10; i++)
> +		im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;

Empty line, please.



Thanks.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Philosophy:  A route of many roads leading from nowhere to nothing.
- Ambrose Bierce


More information about the U-Boot mailing list