[U-Boot] [PATCH] 83xx: Fix some bugs in spd sdram code

[Joakim Tjernlund]

> 
> > > 1. RD_TO_PRE missed to add the AL, and need min 2 clocks for
> > >   tRTP according to DDR2 JEDEC spec.
> > > 2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec.
> > > 3. add the support of DDR2-533,667,800 DIMMs
> > > 4. cpo
> > > 5. make the AL to min to gain better performance.
> > > 
> > > The Micron MT9HTF6472CHY-667D1 DIMMs test passed on
> > > MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.
> > > 
> > > Reported-by: Joakim Tjernlund <Joakim.Tjernlund at transmode.se>
> > > Signed-off-by: Dave Liu <daveliu at freescale.com>
> > 
> > 1, 2 and 5
> > Acked-by: Joakim Tjernlund <Joakim.Tjernlund at transmode.se>
> > 
> > Don't understand cpo and haven't looked at 3 so
> > I can't say anything useful.
> 
> Did you test the patch on your board?
> Have a try... Give me the result.

I wish I could, but I am still on an older version of u-boot and have
not ported it to main stream yet. Tried but it was non trivial so
it have to wait for the moment.

> 
> The code actually is ugly. The max operation freq of the whole
> 83xx DDR controller is lagging the mainstream DDR2 DIMMs.
> We have to put the high speed DIMMs to low speed controller.
> It sounds like ugly. So we often happen the boundary issue.
> 
> Basically, the mainstream PC industry DDR2 DIMMs is DDR2-667
> DDR2-800, and it is shifting to DDR3 technology.
> However, the max data rate for 83xx family is 400MHz.

hmm, are there 832x that can do 400 MHz?
We are using 266 ATM.