[U-Boot] [PATCH] 83xx: Fix some bugs in spd sdram code

Liu Dave-R63238 DaveLiu at freescale.com
Wed Feb 25 10:38:14 CET 2009


> > The code actually is ugly. The max operation freq of the whole 83xx 
> > DDR controller is lagging the mainstream DDR2 DIMMs.
> > We have to put the high speed DIMMs to low speed controller.
> > It sounds like ugly. So we often happen the boundary issue.
> > 
> > Basically, the mainstream PC industry DDR2 DIMMs is 
> DDR2-667 DDR2-800, 
> > and it is shifting to DDR3 technology.
> > However, the max data rate for 83xx family is 400MHz.
> 
> hmm, are there 832x that can do 400 MHz?
> We are using 266 ATM.

No. 832x can support max 266MHz data rate from H/W spec.


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