[U-Boot] [PATCH 5/5] P2020RDB Platform support added.

Kumar Gala galak at kernel.crashing.org
Thu Jul 2 15:59:52 CEST 2009


>
>
> index acec1a0..21eb424 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1,4 +1,5 @@
> #
> +# Copyright (C) 2009 Freescale Semiconductor, Inc. All rights  
> reserved.
> # (C) Copyright 2000-2009
> # Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> #
> @@ -2491,6 +2492,13 @@ P2020DS_config:		unconfig
> 	fi
> 	@$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale
>
> +P2020RDB_config:	unconfig
> +	@mkdir -p $(obj)include
> +	@echo "#define CONFIG_MP" >>$(obj)include/config.h ;
> +	@$(XECHO) "... setting CONFIG_MP." ;

what's going on here?  Why not just set CONFIG_MP in include/configs/ 
P1_P2_RDB.h

> +	@echo "#define CONFIG_P2020" >>$(obj)include/config.h ;
> +	@$(MKCONFIG) -a P1_P2_RDB  ppc mpc85xx p1_p2_rdb freescale
> +
> PM854_config:	unconfig
> 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
>

>
> diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/ 
> p1_p2_rdb/p1_p2_rdb.c
> new file mode 100644
> index 0000000..15520cc
> --- /dev/null
> +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
> @@ -0,0 +1,526 @@
> +/*
> + * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights  
> reserved.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <pci.h>
> +#include <asm/processor.h>
> +#include <asm/mmu.h>
> +#include <asm/cache.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/fsl_pci.h>
> +#include <asm/fsl_ddr_sdram.h>
> +#include <asm/io.h>
> +#include <asm/fsl_law.h>
> +#include <miiphy.h>
> +#include <libfdt.h>
> +#include <fdt_support.h>
> +#include <tsec.h>
> +#include <vsc7385.h>

Can we split out the ddr code into ddr.c and the pci code into pci.c

>
> +
> +
> +#if defined(CONFIG_DDR_ECC) && ! 
> defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> +extern void ddr_enable_ecc(unsigned int dram_size);
> +#endif
> +
> +#define GPIO_DIR	0x060f0000
> +#define BOARD_PERI_RST	0x020f0000
> +#define USB_RST		0x08000000
> +
> +#define SYSCLK_MASK	0x00200000
> +#define BOARDREV_MASK	0x10100000
> +#define BOARDREV_B	0x10100000
> +#define BOARDREV_C	0x00100000
> +
> +#define SYSCLK_66	66666666
> +#define SYSCLK_50	50000000
> +#define SYSCLK_100	100000000
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +phys_size_t  fixed_sdram(void);
> +
> +unsigned long get_board_sys_clk(ulong dummy)
> +{
> +	volatile ccsr_gpio_t *pgpio = (void *) 
> (CONFIG_SYS_MPC85xx_GPIO_ADDR);
> +	u32 val, sysclk, temp;
> +
> +	val = pgpio->gpdat;
> +	sysclk = val & SYSCLK_MASK;
> +	temp = val & BOARDREV_MASK;
> +	if (temp == BOARDREV_C) {
> +		if(sysclk == 0)
> +			return SYSCLK_66;
> +		else
> +			return SYSCLK_100;
> +	} else if (temp == BOARDREV_B) {
> +		if(sysclk == 0)
> +			return SYSCLK_66;
> +		else
> +			return SYSCLK_50;
> +	}
> +}
> +
> +unsigned long get_board_ddr_size(ulong dummy)
> +{
> +	return 1024;
> +}
> +
> +int board_early_init_f (void)
> +{
> +#ifdef CONFIG_MMC
> +	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +
> +	setbits_be32(&gur->pmuxcr,
> +			(MPC85xx_PMUXCR_SDHC_CD |
> +			 MPC85xx_PMUXCR_SDHC_WP));
> +#endif
> +	return 0;
> +}
> +
> +int checkboard (void)
> +{
> +	u32 val, temp;
> +	volatile ccsr_gpio_t *pgpio = (void *) 
> (CONFIG_SYS_MPC85xx_GPIO_ADDR);
> +	char board_rev = 0;
> +
> +	val = pgpio->gpdat;
> +	temp = val & BOARDREV_MASK;
> +	if (temp == BOARDREV_C)
> +		board_rev = 'C';
> +	else if (temp == BOARDREV_B)
> +		board_rev = 'B';
> +
> +	printf ("Board: %sRDB Rev%c, System ID: 0x%02x, "
> +		"System Version: 0x%02x\n", gd->cpu->name,
> +						board_rev, 0, 0);
> +
> +/* Bringing the following peripherals out of reset via GPIOs
> + * 0= reset and 1= out of reset
> + * GPIO12 - Reset to Ethernet Switch
> + * GPIO13 - Reset to SLIC/SLAC devices
> + * GPIO14 - Reset to SGMII_PHY_N
> + * GPIO15 - Reset to PCIe slots
> + * GPIO6  - Reset to RGMII PHY
> + * GPIO5 - Reset to USB3300 devices 1= reset and 0= out of reset
> + */
> +	val = pgpio->gpdir;
> +	val |=  GPIO_DIR;
> +	setbits_be32(&pgpio->gpdir, GPIO_DIR);
> +
> +	val = pgpio->gpdat;
> +	clrsetbits_be32(&pgpio->gpdat, USB_RST, BOARD_PERI_RST);
> +
> +	return 0;
> +}
> +
> +phys_size_t initdram(int board_type)
> +{
> +	phys_size_t dram_size = 0;
> +
> +	puts("Initializing....");
> +
> +#ifdef CONFIG_DDR_SPD
> +	dram_size = fsl_ddr_sdram();
> +#else
> +	dram_size = fixed_sdram();
> +	set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
> +#endif
> +	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
> +	dram_size *= 0x100000;
> +
> +#if defined(CONFIG_DDR_ECC) && ! 
> defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> +	/*
> +	 * Initialize and enable DDR ECC.
> +	 */
> +	ddr_enable_ecc(dram_size);
> +#endif
> +	puts("    DDR: ");
> +	return dram_size;
> +}
> +
> +#if !defined(CONFIG_SPD)
> +/*
> + * Fixed sdram init -- doesn't use serial presence detect.
> + */
> +
> +phys_size_t fixed_sdram (void)
> +{
> +
> +	volatile ccsr_ddr_t *ddr= (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
> +	int d_init;
> +	sys_info_t sysinfo;
> +	char buf[32];
> +
> +	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
> +	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
> +	ddr->cs0_config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2;
> +	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
> +
> +	get_sys_info(&sysinfo);
> +	printf("Configuring DDR for %s MT/s data rate\n",
> +				strmhz(buf, sysinfo.freqDDRBus));
> +
> +	if(sysinfo.freqDDRBus <= 400000000) {
> +		/* RevB and RevC boards */
> +		ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400;
> +		ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400;
> +		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400;
> +		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400;
> +		ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4_400;
> +		ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5_400;
> +		ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1_400;
> +		ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400;
> +		ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL_400;
> +		ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400;
> +		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_400;
> +		ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2_400;
> +	}
> +	else if(sysinfo.freqDDRBus <= 534000000) {
> +		ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533;
> +		ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533;
> +		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533;
> +		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533;
> +		ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4_533;
> +		ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5_533;
> +		ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1_533;
> +		ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533;
> +		ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL_533;
> +		ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533;
> +		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_533;
> +		ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2_533;
> +	}
> +	else if(sysinfo.freqDDRBus <= 667000000) {
> +		ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667;
> +		ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667;
> +		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667;
> +		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667;
> +		ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4_667;
> +		ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5_667;
> +		ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1_667;
> +		ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667;
> +		ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL_667;
> +		ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667;
> +		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_667;
> +		ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2_667;
> +	}
> +	else if(sysinfo.freqDDRBus <= 800000000) {
> +		ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800;
> +		ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800;
> +		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800;
> +		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800;
> +		ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4_800;
> +		ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5_800;
> +		ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1_800;
> +		ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800;
> +		ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL_800;
> +		ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800;
> +		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_800;
> +		ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2_800;
> +	}
> +
> +	/*
> +	 * For 8572 DDR1 erratum - DDR controller may enter illegal state
> +	 * when operatiing in 32-bit bus mode with 4-beat bursts,
> +	 * This erratum does not affect DDR3 mode, only for DDR2 mode.
> +	 * need to check if this is required for P1020/P2020 also
> +	 */
> +        if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) ==  
> SDRAM_TYPE_DDR2)
> +            && in_be32(&ddr->sdram_cfg) & 0x80000) {
> +                /* set DEBUG_1[31] */
> +                u32 temp = in_be32(&ddr->debug_1);
> +                out_be32(&ddr->debug_1, temp | 1);
> +        }
> +
> +#if defined (CONFIG_DDR_ECC)
> +	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
> +	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
> +	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
> +#endif
> +	asm("sync;isync");
> +
> +	udelay(500);
> +
> +	ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
> +
> +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> +	d_init = 1;
> +	debug("DDR - 1st controller: memory initializing\n");
> +	/*
> +	 * Poll until memory is initialized.
> +	 * 512 Meg at 400 might hit this 200 times or so.
> +	 */
> +	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
> +		udelay(1000);
> +	}
> +	debug("DDR: memory initialized\n\n");
> +	asm("sync; isync");
> +	udelay(500);
> +#endif
> +
> +	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
> +}
> +
> +#endif
> +
> +#ifdef CONFIG_PCIE1
> +static struct pci_controller pcie1_hose;
> +#endif
> +
> +#ifdef CONFIG_PCIE2
> +static struct pci_controller pcie2_hose;
> +#endif
> +
> +int first_free_busno=0;
> +#ifdef CONFIG_PCI
> +void pci_init_board(void)
> +{
> +	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +	uint devdisr = gur->devdisr;
> +	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
> +	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
> +
> +	volatile ccsr_fsl_pci_t *pci;
> +	struct pci_controller *hose;
> +	int pcie_ep, pcie_configured;
> +	struct pci_region *r;
> +/*              u32 temp32; */

remove this since its not used

>
> +
> +	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
> +			devdisr, io_sel, host_agent);
> +
> +	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
> +		printf ("    eTSEC2 is in sgmii mode.\n");
> +
> +#ifdef CONFIG_PCIE2
> +	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
> +	hose = &pcie2_hose;
> +	pcie_ep = (host_agent == 2) || (host_agent == 4) ||
> +		(host_agent == 6) || (host_agent == 0);
> +	pcie_configured  = (io_sel == 0xE);
> +	r = hose->regions;
> +
> +	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
> +		printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
> +				pcie_ep ? "End Point" : "Root Complex",
> +				(uint)pci);
> +		if (pci->pme_msg_det) {
> +			pci->pme_msg_det = 0xffffffff;
> +			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
> +		}
> +		printf ("\n");
> +
> +		/* inbound */
> +		r += fsl_pci_setup_inbound_windows(r);
> +
> +		/* outbound memory */
> +		pci_set_region(r++,
> +				CONFIG_SYS_PCIE2_MEM_BUS,
> +				CONFIG_SYS_PCIE2_MEM_PHYS,
> +				CONFIG_SYS_PCIE2_MEM_SIZE,
> +				PCI_REGION_MEM);
> +
> +		/* outbound io */
> +		pci_set_region(r++,
> +				CONFIG_SYS_PCIE2_IO_BUS,
> +				CONFIG_SYS_PCIE2_IO_PHYS,
> +				CONFIG_SYS_PCIE2_IO_SIZE,
> +				PCI_REGION_IO);
> +
> +		hose->region_count = r - hose->regions;
> +		hose->first_busno=first_free_busno;
> +		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci- 
> >cfg_data);
> +
> +		fsl_pci_init(hose);
> +		first_free_busno=hose->last_busno+1;
> +		printf ("    PCIE2 on bus %02x - %02x\n",
> +				hose->first_busno,hose->last_busno);
> +
> +	} else {
> +		printf ("    PCIE2: disabled\n");
> +	}
> +#else
> +	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
> +#endif
> +#ifdef CONFIG_PCIE1
> +	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
> +	hose = &pcie1_hose;
> +	pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
> +		(host_agent == 5);
> +	pcie_configured  = (io_sel == 0xE);
> +	r = hose->regions;
> +
> +	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
> +		printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
> +				pcie_ep ? "End Point" : "Root Complex",
> +				(uint)pci);
> +		if (pci->pme_msg_det) {
> +			pci->pme_msg_det = 0xffffffff;
> +			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
> +		}
> +		printf ("\n");
> +
> +		/* inbound */
> +		r += fsl_pci_setup_inbound_windows(r);
> +
> +		/* outbound memory */
> +		pci_set_region(r++,
> +				CONFIG_SYS_PCIE1_MEM_BUS,
> +				CONFIG_SYS_PCIE1_MEM_PHYS,
> +				CONFIG_SYS_PCIE1_MEM_SIZE,
> +				PCI_REGION_MEM);
> +
> +		/* outbound io */
> +		pci_set_region(r++,
> +				CONFIG_SYS_PCIE1_IO_BUS,
> +				CONFIG_SYS_PCIE1_IO_PHYS,
> +				CONFIG_SYS_PCIE1_IO_SIZE,
> +				PCI_REGION_IO);
> +
> +		hose->region_count = r - hose->regions;
> +		hose->first_busno=first_free_busno;
> +
> +		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci- 
> >cfg_data);
> +
> +		fsl_pci_init(hose);
> +
> +		first_free_busno=hose->last_busno+1;
> +		printf("    PCIE1 on bus %02x - %02x\n",
> +				hose->first_busno,hose->last_busno);
> +
> +	} else {
> +		printf ("    PCIE1: disabled\n");
> +	}
> +#else
> +	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
> +#endif
> +}
> +#endif
> +
> +int board_early_init_r(void)
> +{
> +	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
> +	const u8 flash_esel = 2;
> +
> +	/*
> +	 * Remap Boot flash region to caching-inhibited
> +	 * so that flash can be erased properly.
> +	 */
> +
> +	/* Flush d-cache and invalidate i-cache of any FLASH data */
> +	flush_dcache();
> +	invalidate_icache();
> +
> +	/* invalidate existing TLB entry for flash */
> +	disable_tlb(flash_esel);
> +
> +	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn  
> */
> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
> +			0, flash_esel, BOOKE_PAGESZ_16M, 1);	/* ts, esel, tsize, iprot */
> +	return 0;
> +}
> +
> +
> +#ifdef CONFIG_TSEC_ENET
> +int board_eth_init(bd_t *bis)
> +{
> +	struct tsec_info_struct tsec_info[4];
> +	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +	int num = 0;
> +
> +#ifdef CONFIG_TSEC1
> +	SET_STD_TSEC_INFO(tsec_info[num], 1);
> +	num++;
> +#endif
> +#ifdef CONFIG_TSEC2
> +	SET_STD_TSEC_INFO(tsec_info[num], 2);
> +	num++;
> +#endif
> +#ifdef CONFIG_TSEC3
> +	SET_STD_TSEC_INFO(tsec_info[num], 3);
> +	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
> +		tsec_info[num].flags |= TSEC_SGMII;
> +	num++;
> +#endif
> +
> +	if (!num) {
> +		printf("No TSECs initialized\n");
> +
> +		return 0;
> +	}
> +
> +	tsec_eth_init(bis, tsec_info, num);
> +
> +	return 0;

change to         return pci_eth_init(bis);

>
> +}
> +#endif
> +
> +/*
> + * Miscellaneous late-boot configurations
> + *
> + * If a VSC7385 microcode image is present, then upload it.
> +*/
> +int misc_init_r(void)
> +{
> +	int rc = 0;
> +
> +
> +#ifdef CONFIG_VSC7385_IMAGE
> +	printf(" uploading VSC7385 microcode.from %x\n",  
> CONFIG_VSC7385_IMAGE);
> +	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
> +					CONFIG_VSC7385_IMAGE_SIZE)) {
> +		puts("Failure uploading VSC7385 microcode.\n");
> +		rc = 1;
> +	}
> +#endif
> +
> +	return rc;
> +}
> +
> +#if defined(CONFIG_OF_BOARD_SETUP)
> +void ft_board_setup(void *blob, bd_t *bd)
> +{
> +	ulong base, size;

these need to be:
	phys_addr_t base;
	phys_size_t size;

>
> +
> +	ft_cpu_setup(blob, bd);
> +
> +	base = getenv_bootm_low();
> +	size = getenv_bootm_size();
> +
> +	fdt_fixup_memory(blob, (u64)base, (u64)size);
> +
> +#ifdef CONFIG_PCIE2
> +	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
> +#endif
> +#ifdef CONFIG_PCIE1
> +	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
> +#endif
> +}
> +#endif
> +
> +#ifdef CONFIG_MP
> +extern void cpu_mp_lmb_reserve(struct lmb *lmb);
> +
> +void board_lmb_reserve(struct lmb *lmb)
> +{
> +	cpu_mp_lmb_reserve(lmb);
> +}
> +#endif


> diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
> new file mode 100644
> index 0000000..f740db5
> --- /dev/null
> +++ b/include/configs/P1_P2_RDB.h
> @@ -0,0 +1,623 @@
> +/*
> + * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights  
> reserved.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * P1 P2 RDB board configuration file
> + * This file is intends to address a set of Low End and Ultra Low End
> + * Freescale SOCs of QorIQ series(RDB platforms).
> + * Currently only P2020RDB
> + *
> + */
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/* High Level Configuration Options */
> +#define CONFIG_BOOKE		1	/* BOOKE */
> +#define CONFIG_E500		1	/* BOOKE e500 family */
> +#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020, etc */
> +#define CONFIG_FSL_ELBC	1	/* Enable eLBC Support */
> +#define CONFIG_PCI		1	/* Enable PCI/PCIE */
> +#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
> +#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
> +#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
> +#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
> +#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
> +#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
> +#define CONFIG_TSEC_ENET		/* tsec ethernet support */
> +#define CONFIG_ENV_OVERWRITE
> +
> +
> +#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /*sysclk for P1_P2  
> RDB */
> +#define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on P1_P2 RDB */
> +
> +/*
> + * These can be toggled for performance analysis, otherwise use  
> default.
> + */
> +#define CONFIG_L2_CACHE			/* toggle L2 cache */
> +#define CONFIG_BTB			/* toggle branch predition */
> +
> +#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
> +
> +#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
> +
> +#define CONFIG_ENABLE_36BIT_PHYS	1
> +
> +#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
> +#define CONFIG_SYS_MEMTEST_END		0x1fffffff
> +#define CONFIG_PANIC_HANG	/* do not reset board on panic */
> +
> +/*
> + * Base addresses -- Note these are effective addresses where the
> + * actual resources get mapped (not physical addresses)
> + */
> +#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
> +#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
> +#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr  
> of CCSRBAR */
> +#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses  
> CONFIG_SYS_IMMR */
> +
> +#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
> +#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
> +
> +/* DDR Setup */
> +#define CONFIG_FSL_DDR2
> +#undef CONFIG_FSL_DDR_INTERACTIVE
> +#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
> +/*							on the board */
> +#undef CONFIG_DDR_DLL
> +
> +#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
> +
> +#define CONFIG_SYS_SDRAM_SIZE		get_board_ddr_size(0)
> +#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
> +#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
> +
> +#define CONFIG_NUM_DDR_CONTROLLERS	1
> +#define CONFIG_DIMM_SLOTS_PER_CTLR	1
> +#define CONFIG_CHIP_SELECTS_PER_CTRL	1
> +
> +/* These are used when DDR doesn't use SPD.  */
> +/* DDR2 at 533MHz, 512MB */
> +#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
> +#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202	/* Enable, no  
> interleaving */
> +#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
> +
> +#define CONFIG_SYS_DDR_TIMING_3_533		0x00020000
> +#define CONFIG_SYS_DDR_TIMING_0_533		0x00260802
> +#define CONFIG_SYS_DDR_TIMING_1_533		0x4c47c432
> +#define CONFIG_SYS_DDR_TIMING_2_533		0x0f9848ce
> +#define CONFIG_SYS_DDR_TIMING_4_533		0x00000000
> +#define CONFIG_SYS_DDR_TIMING_5_533		0x00000000
> +#define CONFIG_SYS_DDR_CLK_CTRL_533		0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_533		0x00040642
> +#define CONFIG_SYS_DDR_MODE_2_533		0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_533		0x08200100
> +#define CONFIG_SYS_DDR_CONTROL_533		0x43000000	/* Type = DDR2 */
> +#define CONFIG_SYS_DDR_CONTROL2_533		0x24401000
> +
> +
> +#define CONFIG_SYS_DDR_TIMING_3_400		0x00010000
> +#define CONFIG_SYS_DDR_TIMING_0_400		0x00260802
> +#define CONFIG_SYS_DDR_TIMING_1_400		0x39355322
> +#define CONFIG_SYS_DDR_TIMING_2_400		0x1f9048ca
> +#define CONFIG_SYS_DDR_TIMING_4_400		0x00000000
> +#define CONFIG_SYS_DDR_TIMING_5_400		0x00000000
> +#define CONFIG_SYS_DDR_CLK_CTRL_400		0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_400		0x00480432
> +#define CONFIG_SYS_DDR_MODE_2_400		0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_400		0x06180100
> +#define CONFIG_SYS_DDR_CONTROL_400		0x43000000	/* Type = DDR2 */
> +#define CONFIG_SYS_DDR_CONTROL2_400		0x24401000
> +
> +
> +#define CONFIG_SYS_DDR_TIMING_3_667		0x00030000
> +#define CONFIG_SYS_DDR_TIMING_0_667		0x55770802
> +#define CONFIG_SYS_DDR_TIMING_1_667		0x5f599543
> +#define CONFIG_SYS_DDR_TIMING_2_667		0x0fa074d1
> +#define CONFIG_SYS_DDR_TIMING_4_667		0x00000000
> +#define CONFIG_SYS_DDR_TIMING_5_667		0x00000000
> +#define CONFIG_SYS_DDR_CLK_CTRL_667		0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_667		0x00040852
> +#define CONFIG_SYS_DDR_MODE_2_667		0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_667		0x0a280100
> +#define CONFIG_SYS_DDR_CONTROL_667		0x43000000	/* Type = DDR2 */
> +#define CONFIG_SYS_DDR_CONTROL2_667		0x24401000
> +
> +#define CONFIG_SYS_DDR_TIMING_3_800		0x00040000
> +#define CONFIG_SYS_DDR_TIMING_0_800		0x55770802
> +#define CONFIG_SYS_DDR_TIMING_1_800		0x6f6b6543
> +#define CONFIG_SYS_DDR_TIMING_2_800		0x0fa074d1
> +#define CONFIG_SYS_DDR_TIMING_4_800		0x00000000
> +#define CONFIG_SYS_DDR_TIMING_5_800		0x00000000
> +#define CONFIG_SYS_DDR_CLK_CTRL_800		0x02000000
> +#define CONFIG_SYS_DDR_MODE_1_800			0x00440862
> +#define CONFIG_SYS_DDR_MODE_2_800			0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_800		0x0a280100
> +#define CONFIG_SYS_DDR_CONTROL_800			0x43000000	/* Type = DDR2 */
> +#define CONFIG_SYS_DDR_CONTROL2_800		0x24401000
> +
> +#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
> +#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
> +#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
> +
> +#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
> +#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
> +#define CONFIG_SYS_DDR_SBE		0x00FF0000
> +
> +#define CONFIG_SYS_DDR_TLB_START 9
> +
> +#undef CONFIG_CLOCKS_IN_MHZ
> +
> +/*
> + * Memory map
> + *
> + * 0x0000_0000	0x3fff_ffff	DDR			1G cacheablen
> + * 0xa000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
> + * 0xffc2_0000	0xffc5_ffff	PCI IO range		256K non-cacheable
> + *
> + * Localbus cacheable (TBD)
> + * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
> + *
> + * Localbus non-cacheable
> + * 0xef00_0000	0xefff_ffff	FLASH			16M non-cacheable
> + * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
> + * 0xffb0_0000	0xffbf_ffff	VSC7385 switch		1M non-cacheable
> + * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
> + * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
> + */
> +
> +/*
> + * Local Bus Definitions
> + */
> +#define CONFIG_SYS_FLASH_BASE		0xef000000	/* start of FLASH 16M */
> +
> +#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
> +
> +#define CONFIG_FLASH_BR_PRELIM	 
> (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
> +#define CONFIG_FLASH_OR_PRELIM		0xff000ff7

We have OR_ bitmasks

>
> +
> +#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
> +#define CONFIG_SYS_FLASH_QUIET_TEST
> +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1  
> */
> +
> +#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
> +#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
> +#undef	CONFIG_SYS_FLASH_CHECKSUM
> +#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout  
> (ms) */
> +#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout  
> (ms) */
> +
> +#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
> +
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_SYS_FLASH_EMPTY_INFO
> +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
> +
> +#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r  
> function */
> +
> +
> +#define CONFIG_SYS_INIT_RAM_LOCK	1
> +#define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000	/* stack in RAM */

fix whitespace

>
> +#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in  
> RAM */
> +
> +#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
> +#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END -  
> CONFIG_SYS_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
> +
> +#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for  
> Mon */
> +#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc  
> */
> +
> +#define CONFIG_SYS_NAND_BASE		0xffa00000
> +#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
> +#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
> +#define CONFIG_SYS_MAX_NAND_DEVICE	1
> +#define NAND_MAX_CHIPS	1
> +#define CONFIG_MTD_NAND_VERIFY_WRITE
> +#define CONFIG_CMD_NAND	1
> +#define CONFIG_NAND_FSL_ELBC	1
> +#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
> +
> +/* NAND flash config */
> +#define CONFIG_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
> +				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
> +				| BR_PS_8		/* Port Size = 8 bit */ \
> +				| BR_MS_FCM		/* MSEL = FCM */ \
> +				| BR_V)			/* valid */
> +
> +#define CONFIG_NAND_OR_PRELIM	(0xFFF80000		/* length 32K */ \
> +				| OR_FCM_CSCT \
> +				| OR_FCM_CST \
> +				| OR_FCM_CHT \
> +				| OR_FCM_SCY_1 \
> +				| OR_FCM_TRLX \
> +				| OR_FCM_EHTR)
> +
> +#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base  
> Address */
> +#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR  
> Options */
> +#define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base  
> Address */
> +#define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND  
> Options */
> +
> +#define CONFIG_SYS_VSC7385_BASE	0xffb00000
> +
> +#define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
> +
> +#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_VSC7385_BASE | BR_PS_8 |  
> BR_V) /* VSC7385 switch */
> +#define CONFIG_SYS_OR2_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT |  
> OR_GPCM_XACS | \
> +				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
> +				OR_GPCM_EHTR | OR_GPCM_EAD)
> +
> +/* Serial Port - controlled on board with jumper J8
> + * open - index 2
> + * shorted - index 1
> + */
> +#define CONFIG_CONS_INDEX	1
> +//#define CONFIG_CONS_INDEX	2
> +#undef	CONFIG_SERIAL_SOFTWARE_FIFO
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE	1
> +#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
> +
> +#define CONFIG_SERIAL_MULTI	1 /* Enable both serial ports */
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
> +
> +#define CONFIG_SYS_BAUDRATE_TABLE	\
> +	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
> +
> +#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
> +#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
> +
> +/* Use the HUSH parser */
> +#define CONFIG_SYS_HUSH_PARSER
> +#ifdef	CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#endif
> +
> +/*
> + * Pass open firmware flat tree
> + */
> +#define CONFIG_OF_LIBFDT		1
> +#define CONFIG_OF_BOARD_SETUP		1
> +#define CONFIG_OF_STDOUT_VIA_ALIAS	1
> +
> +#define CONFIG_SYS_64BIT_VSPRINTF	1
> +#define CONFIG_SYS_64BIT_STRTOUL	1
> +
> +/* new uImage format support */
> +#define CONFIG_FIT		1
> +#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}()  
> */
> +
> +/* I2C */
> +#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
> +#define CONFIG_HARD_I2C		/* I2C with hardware support */
> +#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
> +#define CONFIG_I2C_MULTI_BUS
> +#define CONFIG_I2C_CMD_TREE
> +#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address  
> */
> +#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
> +#define CONFIG_SYS_I2C_SLAVE		0x7F
> +#define CONFIG_SYS_I2C_NOPROBES	{{0,0x29}}/* Don't probe these  
> addrs */
> +#define CONFIG_SYS_I2C_OFFSET		0x3000
> +#define CONFIG_SYS_I2C2_OFFSET		0x3100
> +
> +/*
> + * I2C2 EEPROM
> + */
> +#define CONFIG_ID_EEPROM
> +#ifdef CONFIG_ID_EEPROM
> +#define CONFIG_SYS_I2C_EEPROM_NXID
> +#endif
> +#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
> +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
> +#define CONFIG_SYS_EEPROM_BUS_NUM	1
> +
> +//#define CONFIG_RTC_DS1337
> +/*
> + * General PCI
> + * Memory space is mapped 1-1, but I/O space must start from 0.
> + */
> +
> +/* controller 2, Slot 2, tgtid 2, Base address 9000 */
> +#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
> +#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
> +#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
> +#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
> +#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
> +#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
> +#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
> +#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
> +
> +/* controller 1, Slot 1, tgtid 1, Base address a000 */
> +#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
> +#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
> +#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
> +#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
> +#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc30000
> +#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
> +#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc30000
> +#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
> +
> +#if defined(CONFIG_PCI)
> +#define CONFIG_NET_MULTI
> +#define CONFIG_PCI_PNP			/* do pci plug-and-play */
> +
> +#undef CONFIG_EEPRO100
> +#undef CONFIG_TULIP
> +#undef CONFIG_RTL8139
> +
> +#ifdef CONFIG_RTL8139
> +/* This macro is used by RTL8139 but not defined in PPC  
> architecture */
> +#define KSEG1ADDR(x)		(x)
> +#define _IO_BASE	0x00000000

I think Timur posted a patch to remove this
>
> +#endif
> +
> +
> +#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
> +#define CONFIG_DOS_PARTITION
> +
> +#endif	/* CONFIG_PCI */
> +
> +#define CONFIG_MISC_INIT_R
> +
> +/************************************************************
> + * USB support
> + ************************************************************/
> +
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_USB
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_FSL
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +
> +#if defined(CONFIG_TSEC_ENET)
> +
> +#ifndef CONFIG_NET_MULTI
> +#define CONFIG_NET_MULTI	1
> +#endif
> +
> +#define CONFIG_MII		1	/* MII PHY management */
> +#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
> +#define CONFIG_TSEC1	1
> +#define CONFIG_TSEC1_NAME	"eTSEC1"
> +#define CONFIG_TSEC2	1
> +#define CONFIG_TSEC2_NAME	"eTSEC2"
> +#define CONFIG_TSEC3	1
> +#define CONFIG_TSEC3_NAME	"eTSEC3"
> +
> +#define TSEC1_PHY_ADDR		2
> +#define TSEC2_PHY_ADDR		0
> +#define TSEC3_PHY_ADDR		1
> +
> +#define CONFIG_VSC7385_ENET
> +
> +#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
> +#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
> +#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
> +
> +#define TSEC1_PHYIDX		0
> +#define TSEC2_PHYIDX		0
> +#define TSEC3_PHYIDX		0
> +
> +/* Vitesse 7385 */
> +
> +#ifdef CONFIG_VSC7385_ENET
> +
> +/* The flash address and size of the VSC7385 firmware image */
> +#define CONFIG_VSC7385_IMAGE		0xEF000000
> +#define CONFIG_VSC7385_IMAGE_SIZE	8192
> +
> +#endif
> +#define CONFIG_ETHPRIME		"eTSEC1"
> +
> +#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
> +#endif	/* CONFIG_TSEC_ENET */
> +
> +/*
> + * Environment
> + */
> +#define CONFIG_ENV_IS_IN_FLASH	1
> +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
> +#define CONFIG_ENV_ADDR		0xfff80000
> +#else
> +#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE -  
> CONFIG_ENV_SECT_SIZE)
> +#endif
> +#define CONFIG_ENV_SIZE		0x2000
> +#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
> +
> +#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
> +#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_IRQ
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_IRQ
> +#define CONFIG_CMD_SETEXPR
> +
> +#if defined(CONFIG_PCI)
> +#define CONFIG_CMD_PCI
> +#define CONFIG_CMD_BEDBUG
> +#define CONFIG_CMD_NET
> +#endif
> +
> +#undef CONFIG_WATCHDOG			/* watchdog disabled */
> +
> +#define CONFIG_MMC	1
> +
> +#ifdef CONFIG_MMC
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +#ifdef CONFIG_P2020
> +#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not  
> functional*/
> +#endif
> +#endif
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
> +#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
> +#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
> +#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
> +#if defined(CONFIG_CMD_KGDB)
> +#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
> +#else
> +#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
> +#endif
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE 
> +sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
> +#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
> +#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument  
> Buffer Size */
> +#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
> +
> +/*
> + * For booting Linux, the board info and command line data
> + * have to be in the first 8 MB of memory, since this is

8 MB -> 16 MB

>
> + * the maximum mapped by the Linux kernel during initialization.
> + */
> +#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for  
> Linux*/

Make this (16 << 20)
>
> +
> +/*
> + * Internal Definitions
> + *
> + * Boot Flags
> + */
> +#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
> +#define BOOTFLAG_WARM	0x02		/* Software reboot */
> +
> +#if defined(CONFIG_CMD_KGDB)
> +#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial  
> port */
> +#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
> +#endif
> +
> +/*
> + * Environment Configuration
> + */
> +
> +#if defined(CONFIG_TSEC_ENET)
> +#define CONFIG_HAS_ETH0
> +#define CONFIG_HAS_ETH1
> +#define CONFIG_HAS_ETH2
> +#endif
> +
> +#define CONFIG_HOSTNAME		unknown
> +#define CONFIG_ROOTPATH		/opt/nfsroot
> +#define CONFIG_BOOTFILE		uImage
> +#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
> +
> +/* default location for tftp and bootm */
> +#define CONFIG_LOADADDR		1000000
> +
> +#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
> +#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
> +
> +#define CONFIG_BAUDRATE	115200
> +
> +#define	CONFIG_EXTRA_ENV_SETTINGS				\
> + "netdev=eth0\0"						\
> + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
> + "loadaddr=1000000\0"			\
> + "bootfile=uImage\0"	\
> + "tftpflash=tftpboot $loadaddr $uboot; "			\
> +	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
> +	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
> +	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
> +	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
> +	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
> + "consoledev=ttyS0\0"				\
> + "ramdiskaddr=2000000\0"			\
> + "ramdiskfile=rootfs.ext2.gz.uboot\0"		\
> + "fdtaddr=c00000\0"				\
> + "fdtfile=p2020rdb.dtb\0"		\
> + "bdev=sda1\0"	\
> + "jffs2nor=mtdblock3\0"	\
> + "norbootaddr=ef080000\0"	\
> + "norfdtaddr=ef040000\0"	\
> + "jffs2nand=mtdblock9\0"	\
> + "nandbootaddr=100000\0"	\
> + "nandfdtaddr=80000\0"		\
> + "usb_phy_type=ulpi\0"		\
> + "usbfatboot=setenv bootargs root=/dev/ram rw "	\
> + "console=$consoledev,$baudrate $othbootargs "	\
> + "ramdisk_size=120000;"			\
> + "usb start;"			\
> + "fatload usb 0:2 $loadaddr $bootfile;"		\
> + "fatload usb 0:2 $fdtaddr $fdtfile;"	\
> + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
> + "bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
> + "usbext2boot=setenv bootargs root=/dev/ram rw "	\
> + "console=$consoledev,$baudrate $othbootargs "	\
> + "ramdisk_size=120000;"			\
> + "usb start;"			\
> + "ext2load usb 0:4 $loadaddr $bootfile;"		\
> + "ext2load usb 0:4 $fdtaddr $fdtfile;"	\
> + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
> + "bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
> + "norboot=setenv bootargs root=/dev/$jffs2nor rw "	\
> + "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
> + "bootm $norbootaddr - $norfdtaddr\0"		\
> + "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2  
> "	\
> + "console=$consoledev,$baudrate $othbootargs;"	\
> + "nand read 2000000 100000 400000;"	\
> + "nand read 3000000 80000 80000;"	\
> + "bootm 2000000 - 3000000;\0"
> +
> +
> +#define CONFIG_NFSBOOTCOMMAND		\
> + "setenv bootargs root=/dev/nfs rw "	\
> + "nfsroot=$serverip:$rootpath "		\
> + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
> + "console=$consoledev,$baudrate $othbootargs;"	\
> + "tftp $loadaddr $bootfile;"		\
> + "tftp $fdtaddr $fdtfile;"		\
> + "bootm $loadaddr - $fdtaddr"
> +
> +#define CONFIG_HDBOOT			\
> + "setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
> + "console=$consoledev,$baudrate $othbootargs;"	\
> + "usb start;"			\
> + "ext2load usb 0:1 $loadaddr /boot/$bootfile;"		\
> + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
> + "bootm $loadaddr - $fdtaddr"
> +
> +#define CONFIG_RAMBOOTCOMMAND		\
> + "setenv bootargs root=/dev/ram rw "	\
> + "console=$consoledev,$baudrate $othbootargs "	\
> + "ramdisk_size=120000;"			\
> + "tftp $ramdiskaddr $ramdiskfile;"	\
> + "tftp $loadaddr $bootfile;"		\
> + "tftp $fdtaddr $fdtfile;"		\
> + "bootm $loadaddr $ramdiskaddr $fdtaddr"
> +
> +#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
> +
> +#endif	/* __CONFIG_H */
> -- 
> 1.5.6.3
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
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