[U-Boot] DRAM test problem

[Scott Wood]

On Wed, Jul 08, 2009 at 11:23:15AM -0300, Alemao wrote:
> In cpu/mpc83xx/start.S, dcache is enable for stack-in-cache trick:
> 
> 	/* enable and invalidate the data cache */
> 	bl	dcache_enable
> 	sync
> 
> dcache_enable:
> 	mfspr	r3, HID0
> 	li	r5, HID0_DCFI|HID0_DLOCK
> 	andc	r3, r3, r5
> 	mtspr	HID0, r3  /* no invalidate, unlock */
> 	ori	r3, r3, HID0_DCE
> 	ori	r5, r3, HID0_DCFI
> 	mtspr	HID0, r5  /* enable + invalidate */
> 	mtspr	HID0, r3  /* enable */
> 	sync
> 	blr
> 
> 
> I didn't find any code that is disabling it after that.

Did you find anything that unlocks it once the stack-in-cache is no
longer needed?  If not, it will not be usable as a cache, just as a RAM.

-Scott