[U-Boot] [PATCH ARM Clean-up of ARM920T S3C24x0 code
kevin.morfitt at fearnside-systems.co.uk
kevin.morfitt at fearnside-systems.co.uk
Fri Jun 5 20:58:48 CEST 2009
This re-formats the S3C24x0 code in cpu/arm920t and the headers to meet the
coding style requirements and to make it always use the proper I/O accessor
functions when accessing registers. It was done using 'Lindent -kr -i8 -l80'
followed by manual inspection of the output. checkpatch.pl reports no problems
with the patch and I've run MAKEALL for all ARM9 boards with no problems.
This has been done to create a good starting point for me to add support for
a new board, the Embest SBC2440-II. Another patch does the same for the
S3C24x0 drivers code.
Signed-off-by: Kevin Morfitt <kevin.morfitt at fearnside-systems.co.uk>
---
cpu/arm920t/s3c24x0/speed.c | 42 +-
cpu/arm920t/s3c24x0/timer.c | 81 ++--
cpu/arm920t/s3c24x0/usb.c | 22 +-
cpu/arm920t/start.S | 55 +-
include/s3c2400.h | 368 +-----------
include/s3c2410.h | 37 +-
include/s3c24x0.h | 1422 ++++++++++++++-----------------------------
7 files changed, 603 insertions(+), 1424 deletions(-)
diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c
index e0dca62..3d7c8cf 100644
--- a/cpu/arm920t/s3c24x0/speed.c
+++ b/cpu/arm920t/s3c24x0/speed.c
@@ -32,6 +32,8 @@
#include <common.h>
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#include <asm/io.h>
+
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
@@ -53,49 +55,51 @@
static ulong get_PLLCLK(int pllreg)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- ulong r, m, p, s;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ ulong r, m, p, s;
- if (pllreg == MPLL)
- r = clk_power->MPLLCON;
- else if (pllreg == UPLL)
- r = clk_power->UPLLCON;
- else
- hang();
+ if (pllreg == MPLL)
+ r = readl(&clk_power->MPLLCON);
+ else if (pllreg == UPLL)
+ r = readl(&clk_power->UPLLCON);
+ else
+ hang();
- m = ((r & 0xFF000) >> 12) + 8;
- p = ((r & 0x003F0) >> 4) + 2;
- s = r & 0x3;
+ m = ((r & 0xFF000) >> 12) + 8;
+ p = ((r & 0x003F0) >> 4) + 2;
+ s = r & 0x3;
- return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
+ return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
}
/* return FCLK frequency */
ulong get_FCLK(void)
{
- return(get_PLLCLK(MPLL));
+ return get_PLLCLK(MPLL);
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
+ return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
}
/* return PCLK frequency */
ulong get_PCLK(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
+ return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
}
/* return UCLK frequency */
ulong get_UCLK(void)
{
- return(get_PLLCLK(UPLL));
+ return get_PLLCLK(UPLL);
}
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) ||
+ defined (CONFIG_S3C2410) ||
+ defined (CONFIG_TRAB) */
diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c
index f0a09cd..a5a784c 100644
--- a/cpu/arm920t/s3c24x0/timer.c
+++ b/cpu/arm920t/s3c24x0/timer.c
@@ -30,7 +30,11 @@
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#if defined(CONFIG_S3C2400) || \
+ defined(CONFIG_S3C2410) || \
+ defined(CONFIG_TRAB)
+
+#include <asm/io.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
@@ -45,34 +49,37 @@ static inline ulong READ_TIMER(void)
{
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
- return (timers->TCNTO4 & 0xffff);
+ return readl(&timers->TCNTO4) & 0xffff;
}
static ulong timestamp;
static ulong lastdec;
-int timer_init (void)
+int timer_init(void)
{
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ ulong tmr;
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
- timers->TCFG0 = 0x0f00;
- if (timer_load_val == 0)
- {
+ writel(0x0f00, &timers->TCFG0);
+ if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
- timer_load_val = get_PCLK()/(2 * 16 * 100);
+ timer_load_val = get_PCLK() / (2 * 16 * 100);
}
/* load value for 10 ms timeout */
- lastdec = timers->TCNTB4 = timer_load_val;
+ lastdec = timer_load_val;
+ writel(timer_load_val, &timers->TCNTB4);
/* auto load, manual update of Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
+ tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
+ writel(tmr, &timers->TCON);
/* auto load, start Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
+ tmr = (tmr & ~0x0700000) | 0x0500000;
+ writel(tmr, &timers->TCON);
timestamp = 0;
return (0);
@@ -82,22 +89,22 @@ int timer_init (void)
* timer without interrupts
*/
-void reset_timer (void)
+void reset_timer(void)
{
- reset_timer_masked ();
+ reset_timer_masked();
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
- return get_timer_masked () - base;
+ return get_timer_masked() - base;
}
-void set_timer (ulong t)
+void set_timer(ulong t)
{
timestamp = t;
}
-void udelay (unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_timer(0);
@@ -106,18 +113,18 @@ void udelay (unsigned long usec)
tmo *= (timer_load_val * 100);
tmo /= 1000;
- while ((ulong)(get_timer_masked () - start) < tmo)
+ while ((ulong) (get_timer_masked() - start) < tmo)
/*NOP*/;
}
-void reset_timer_masked (void)
+void reset_timer_masked(void)
{
/* reset time */
lastdec = READ_TIMER();
timestamp = 0;
}
-ulong get_timer_masked (void)
+ulong get_timer_masked(void)
{
ulong now = READ_TIMER();
@@ -133,7 +140,7 @@ ulong get_timer_masked (void)
return timestamp;
}
-void udelay_masked (unsigned long usec)
+void udelay_masked(unsigned long usec)
{
ulong tmo;
ulong endtime;
@@ -145,13 +152,13 @@ void udelay_masked (unsigned long usec)
tmo /= 1000;
} else {
tmo = usec * (timer_load_val * 100);
- tmo /= (1000*1000);
+ tmo /= (1000 * 1000);
}
- endtime = get_timer_masked () + tmo;
+ endtime = get_timer_masked() + tmo;
do {
- ulong now = get_timer_masked ();
+ ulong now = get_timer_masked();
diff = endtime - now;
} while (diff >= 0);
}
@@ -169,7 +176,7 @@ unsigned long long get_ticks(void)
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
-ulong get_tbclk (void)
+ulong get_tbclk(void)
{
ulong tbclk;
@@ -189,39 +196,39 @@ ulong get_tbclk (void)
/*
* reset the cpu by setting up the watchdog timer and let him time out
*/
-void reset_cpu (ulong ignored)
+void reset_cpu(ulong ignored)
{
- volatile S3C24X0_WATCHDOG * watchdog;
+ volatile S3C24X0_WATCHDOG *watchdog;
#ifdef CONFIG_TRAB
- extern void disable_vfd (void);
-
disable_vfd();
#endif
watchdog = S3C24X0_GetBase_WATCHDOG();
/* Disable watchdog */
- watchdog->WTCON = 0x0000;
+ writel(0x0000, &watchdog->WTCON);
/* Initialize watchdog timer count register */
- watchdog->WTCNT = 0x0001;
+ writel(0x0001, &watchdog->WTCNT);
/* Enable watchdog timer; assert reset at timer timeout */
- watchdog->WTCON = 0x0021;
+ writel(0x0021, &watchdog->WTCON);
- while(1); /* loop forever and wait for reset to happen */
+ while (1)
+ /* loop forever and wait for reset to happen */;
- /*NOTREACHED*/
-}
+ /*NOTREACHED*/}
#ifdef CONFIG_USE_IRQ
void s3c2410_irq(void)
{
- S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
- u_int32_t intpnd = irq->INTPND;
+ S3C24X0_INTERRUPT *irq = S3C24X0_GetBase_INTERRUPT();
+ u_int32_t intpnd = readl(&irq->INTPND);
}
#endif /* USE_IRQ */
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) ||
+ defined (CONFIG_S3C2410) ||
+ defined (CONFIG_TRAB) */
diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c
index 9ccf575..c2d2f70 100644
--- a/cpu/arm920t/s3c24x0/usb.c
+++ b/cpu/arm920t/s3c24x0/usb.c
@@ -32,9 +32,10 @@
# include <s3c2410.h>
#endif
-int usb_cpu_init (void)
-{
+#include <asm/io.h>
+int usb_cpu_init(void)
+{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
@@ -42,31 +43,32 @@ int usb_cpu_init (void)
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
- clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
- gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+ writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+ /* 1 = use pads related USB for USB host */
+ writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
/*
* Enable USB host clock.
*/
- clk_power->CLKCON |= (1 << 4);
+ writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
return 0;
}
-int usb_cpu_stop (void)
+int usb_cpu_stop(void)
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
/* may not want to do this */
- clk_power->CLKCON &= ~(1 << 4);
+ writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0;
}
-int usb_cpu_init_fail (void)
+int usb_cpu_init_fail(void)
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- clk_power->CLKCON &= ~(1 << 4);
+ writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0;
}
-# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
+# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 475cdaf..810d402 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -38,7 +38,7 @@
.globl _start
-_start: b start_code
+_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -115,8 +115,8 @@ start_code:
orr r0,r0,#0xd3
msr cpsr,r0
- bl coloured_LED_init
- bl red_LED_on
+ bl coloured_LED_init
+ bl red_LED_on
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/*
@@ -136,19 +136,19 @@ copyex:
/* turn off the watchdog */
# if defined(CONFIG_S3C2400)
-# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define pWTCON 0x15300000
+# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
-# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define pWTCON 0x53000000
+# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
- ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
+ ldr r0, =pWTCON
+ mov r1, #0x0
+ str r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
@@ -181,8 +181,8 @@ copyex:
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
@@ -199,8 +199,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -298,8 +298,8 @@ cpu_init_crit:
#define S_R1 4
#define S_R0 0
-#define MODE_SVC 0x13
-#define I_BIT 0x80
+#define MODE_SVC 0x13
+#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
@@ -312,7 +312,8 @@ cpu_init_crit:
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE)
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ /* set base 2 words into abort stack */
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -325,12 +326,12 @@ cpu_init_crit:
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
- add r7, sp, #S_PC
- stmdb r7, {sp, lr}^ @ Calling SP, LR
- str lr, [r7, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r7, #4] @ Save CPSR
- str r0, [r7, #8] @ Save OLD_R0
+ add r7, sp, #S_PC
+ stmdb r7, {sp, lr}^ @ Calling SP, LR
+ str lr, [r7, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r7, #4] @ Save CPSR
+ str r0, [r7, #8] @ Save OLD_R0
mov r0, sp
.endm
@@ -339,18 +340,20 @@ cpu_init_crit:
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ /* return & move spsr_svc into cpsr */
+ subs pc, lr, #4
.endm
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE)
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ /* reserve a couple spots in abort stack */
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
- str lr, [r13, #4]
+ str lr, [r13, #4]
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
diff --git a/include/s3c2400.h b/include/s3c2400.h
index 4fdc62e..fea0d31 100644
--- a/include/s3c2400.h
+++ b/include/s3c2400.h
@@ -62,408 +62,75 @@ typedef enum {
/* include common stuff */
#include <s3c24x0.h>
-
-static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
+static inline S3C24X0_MEMCTL *S3C24X0_GetBase_MEMCTL(void)
{
return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
}
-static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
+static inline S3C24X0_USB_HOST *S3C24X0_GetBase_USB_HOST(void)
{
return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
}
-static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
+static inline S3C24X0_INTERRUPT *S3C24X0_GetBase_INTERRUPT(void)
{
return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
}
-static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
+static inline S3C24X0_DMAS *S3C24X0_GetBase_DMAS(void)
{
return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
}
-static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
+static inline S3C24X0_CLOCK_POWER *S3C24X0_GetBase_CLOCK_POWER(void)
{
return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
}
-static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
+static inline S3C24X0_LCD *S3C24X0_GetBase_LCD(void)
{
return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
}
-static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+static inline S3C24X0_UART *S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
{
return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
}
-static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
+static inline S3C24X0_TIMERS *S3C24X0_GetBase_TIMERS(void)
{
return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
}
-static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
+static inline S3C24X0_USB_DEVICE *S3C24X0_GetBase_USB_DEVICE(void)
{
return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
}
-static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
+static inline S3C24X0_WATCHDOG *S3C24X0_GetBase_WATCHDOG(void)
{
return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
}
-static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
+static inline S3C24X0_I2C *S3C24X0_GetBase_I2C(void)
{
return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
}
-static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
+static inline S3C24X0_I2S *S3C24X0_GetBase_I2S(void)
{
return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
}
-static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
+static inline S3C24X0_GPIO *S3C24X0_GetBase_GPIO(void)
{
return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
}
-static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
+static inline S3C24X0_RTC *S3C24X0_GetBase_RTC(void)
{
return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
}
-static inline S3C2400_ADC * S3C2400_GetBase_ADC(void)
+static inline S3C2400_ADC *S3C2400_GetBase_ADC(void)
{
return (S3C2400_ADC * const)S3C24X0_ADC_BASE;
}
-static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
+static inline S3C24X0_SPI *S3C24X0_GetBase_SPI(void)
{
return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
}
-static inline S3C2400_MMC * S3C2400_GetBase_MMC(void)
+static inline S3C2400_MMC *S3C2400_GetBase_MMC(void)
{
return (S3C2400_MMC * const)S3C2400_MMC_BASE;
}
-#if 0
-/* Memory control */
-#define rBWSCON (*(volatile unsigned *)0x14000000)
-#define rBANKCON0 (*(volatile unsigned *)0x14000004)
-#define rBANKCON1 (*(volatile unsigned *)0x14000008)
-#define rBANKCON2 (*(volatile unsigned *)0x1400000C)
-#define rBANKCON3 (*(volatile unsigned *)0x14000010)
-#define rBANKCON4 (*(volatile unsigned *)0x14000014)
-#define rBANKCON5 (*(volatile unsigned *)0x14000018)
-#define rBANKCON6 (*(volatile unsigned *)0x1400001C)
-#define rBANKCON7 (*(volatile unsigned *)0x14000020)
-#define rREFRESH (*(volatile unsigned *)0x14000024)
-#define rBANKSIZE (*(volatile unsigned *)0x14000028)
-#define rMRSRB6 (*(volatile unsigned *)0x1400002C)
-#define rMRSRB7 (*(volatile unsigned *)0x14000030)
-
-
-/* INTERRUPT */
-#define rSRCPND (*(volatile unsigned *)0x14400000)
-#define rINTMOD (*(volatile unsigned *)0x14400004)
-#define rINTMSK (*(volatile unsigned *)0x14400008)
-#define rPRIORITY (*(volatile unsigned *)0x1440000C)
-#define rINTPND (*(volatile unsigned *)0x14400010)
-#define rINTOFFSET (*(volatile unsigned *)0x14400014)
-
-
-/* DMA */
-#define rDISRC0 (*(volatile unsigned *)0x14600000)
-#define rDIDST0 (*(volatile unsigned *)0x14600004)
-#define rDCON0 (*(volatile unsigned *)0x14600008)
-#define rDSTAT0 (*(volatile unsigned *)0x1460000C)
-#define rDCSRC0 (*(volatile unsigned *)0x14600010)
-#define rDCDST0 (*(volatile unsigned *)0x14600014)
-#define rDMASKTRIG0 (*(volatile unsigned *)0x14600018)
-#define rDISRC1 (*(volatile unsigned *)0x14600020)
-#define rDIDST1 (*(volatile unsigned *)0x14600024)
-#define rDCON1 (*(volatile unsigned *)0x14600028)
-#define rDSTAT1 (*(volatile unsigned *)0x1460002C)
-#define rDCSRC1 (*(volatile unsigned *)0x14600030)
-#define rDCDST1 (*(volatile unsigned *)0x14600034)
-#define rDMASKTRIG1 (*(volatile unsigned *)0x14600038)
-#define rDISRC2 (*(volatile unsigned *)0x14600040)
-#define rDIDST2 (*(volatile unsigned *)0x14600044)
-#define rDCON2 (*(volatile unsigned *)0x14600048)
-#define rDSTAT2 (*(volatile unsigned *)0x1460004C)
-#define rDCSRC2 (*(volatile unsigned *)0x14600050)
-#define rDCDST2 (*(volatile unsigned *)0x14600054)
-#define rDMASKTRIG2 (*(volatile unsigned *)0x14600058)
-#define rDISRC3 (*(volatile unsigned *)0x14600060)
-#define rDIDST3 (*(volatile unsigned *)0x14600064)
-#define rDCON3 (*(volatile unsigned *)0x14600068)
-#define rDSTAT3 (*(volatile unsigned *)0x1460006C)
-#define rDCSRC3 (*(volatile unsigned *)0x14600070)
-#define rDCDST3 (*(volatile unsigned *)0x14600074)
-#define rDMASKTRIG3 (*(volatile unsigned *)0x14600078)
-
-
-/* CLOCK & POWER MANAGEMENT */
-#define rLOCKTIME (*(volatile unsigned *)0x14800000)
-#define rMPLLCON (*(volatile unsigned *)0x14800004)
-#define rUPLLCON (*(volatile unsigned *)0x14800008)
-#define rCLKCON (*(volatile unsigned *)0x1480000C)
-#define rCLKSLOW (*(volatile unsigned *)0x14800010)
-#define rCLKDIVN (*(volatile unsigned *)0x14800014)
-
-
-/* LCD CONTROLLER */
-#define rLCDCON1 (*(volatile unsigned *)0x14A00000)
-#define rLCDCON2 (*(volatile unsigned *)0x14A00004)
-#define rLCDCON3 (*(volatile unsigned *)0x14A00008)
-#define rLCDCON4 (*(volatile unsigned *)0x14A0000C)
-#define rLCDCON5 (*(volatile unsigned *)0x14A00010)
-#define rLCDSADDR1 (*(volatile unsigned *)0x14A00014)
-#define rLCDSADDR2 (*(volatile unsigned *)0x14A00018)
-#define rLCDSADDR3 (*(volatile unsigned *)0x14A0001C)
-#define rREDLUT (*(volatile unsigned *)0x14A00020)
-#define rGREENLUT (*(volatile unsigned *)0x14A00024)
-#define rBLUELUT (*(volatile unsigned *)0x14A00028)
-#define rDP1_2 (*(volatile unsigned *)0x14A0002C)
-#define rDP4_7 (*(volatile unsigned *)0x14A00030)
-#define rDP3_5 (*(volatile unsigned *)0x14A00034)
-#define rDP2_3 (*(volatile unsigned *)0x14A00038)
-#define rDP5_7 (*(volatile unsigned *)0x14A0003c)
-#define rDP3_4 (*(volatile unsigned *)0x14A00040)
-#define rDP4_5 (*(volatile unsigned *)0x14A00044)
-#define rDP6_7 (*(volatile unsigned *)0x14A00048)
-#define rDITHMODE (*(volatile unsigned *)0x14A0004C)
-#define rTPAL (*(volatile unsigned *)0x14A00050)
-#define PALETTE (0x14A00400) /* SJS */
-
-
-/* UART */
-#define rULCON0 (*(volatile unsigned char *)0x15000000)
-#define rUCON0 (*(volatile unsigned short *)0x15000004)
-#define rUFCON0 (*(volatile unsigned char *)0x15000008)
-#define rUMCON0 (*(volatile unsigned char *)0x1500000C)
-#define rUTRSTAT0 (*(volatile unsigned char *)0x15000010)
-#define rUERSTAT0 (*(volatile unsigned char *)0x15000014)
-#define rUFSTAT0 (*(volatile unsigned short *)0x15000018)
-#define rUMSTAT0 (*(volatile unsigned char *)0x1500001C)
-#define rUBRDIV0 (*(volatile unsigned short *)0x15000028)
-
-#define rULCON1 (*(volatile unsigned char *)0x15004000)
-#define rUCON1 (*(volatile unsigned short *)0x15004004)
-#define rUFCON1 (*(volatile unsigned char *)0x15004008)
-#define rUMCON1 (*(volatile unsigned char *)0x1500400C)
-#define rUTRSTAT1 (*(volatile unsigned char *)0x15004010)
-#define rUERSTAT1 (*(volatile unsigned char *)0x15004014)
-#define rUFSTAT1 (*(volatile unsigned short *)0x15004018)
-#define rUMSTAT1 (*(volatile unsigned char *)0x1500401C)
-#define rUBRDIV1 (*(volatile unsigned short *)0x15004028)
-
-#ifdef __BIG_ENDIAN
-#define rUTXH0 (*(volatile unsigned char *)0x15000023)
-#define rURXH0 (*(volatile unsigned char *)0x15000027)
-#define rUTXH1 (*(volatile unsigned char *)0x15004023)
-#define rURXH1 (*(volatile unsigned char *)0x15004027)
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x15000027)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x15004027)
-
-#define UTXH0 (0x15000020+3) /* byte_access address by DMA */
-#define URXH0 (0x15000024+3)
-#define UTXH1 (0x15004020+3)
-#define URXH1 (0x15004024+3)
-
-#else /* Little Endian */
-#define rUTXH0 (*(volatile unsigned char *)0x15000020)
-#define rURXH0 (*(volatile unsigned char *)0x15000024)
-#define rUTXH1 (*(volatile unsigned char *)0x15004020)
-#define rURXH1 (*(volatile unsigned char *)0x15004024)
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x15000024)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x15004024)
-
-#define UTXH0 (0x15000020) /* byte_access address by DMA */
-#define URXH0 (0x15000024)
-#define UTXH1 (0x15004020)
-#define URXH1 (0x15004024)
-#endif
-
-
-/* PWM TIMER */
-#define rTCFG0 (*(volatile unsigned *)0x15100000)
-#define rTCFG1 (*(volatile unsigned *)0x15100004)
-#define rTCON (*(volatile unsigned *)0x15100008)
-#define rTCNTB0 (*(volatile unsigned *)0x1510000C)
-#define rTCMPB0 (*(volatile unsigned *)0x15100010)
-#define rTCNTO0 (*(volatile unsigned *)0x15100014)
-#define rTCNTB1 (*(volatile unsigned *)0x15100018)
-#define rTCMPB1 (*(volatile unsigned *)0x1510001C)
-#define rTCNTO1 (*(volatile unsigned *)0x15100020)
-#define rTCNTB2 (*(volatile unsigned *)0x15100024)
-#define rTCMPB2 (*(volatile unsigned *)0x15100028)
-#define rTCNTO2 (*(volatile unsigned *)0x1510002C)
-#define rTCNTB3 (*(volatile unsigned *)0x15100030)
-#define rTCMPB3 (*(volatile unsigned *)0x15100034)
-#define rTCNTO3 (*(volatile unsigned *)0x15100038)
-#define rTCNTB4 (*(volatile unsigned *)0x1510003C)
-#define rTCNTO4 (*(volatile unsigned *)0x15100040)
-
-
-/* USB DEVICE */
-#define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140)
-#define rPWR_REG (*(volatile unsigned *)0x15200144)
-#define rINT_REG (*(volatile unsigned *)0x15200148)
-#define rINT_MASK_REG (*(volatile unsigned *)0x1520014C)
-#define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150)
-#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154)
-#define rEP0_CSR (*(volatile unsigned *)0x15200160)
-#define rEP0_MAXP (*(volatile unsigned *)0x15200164)
-#define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168)
-#define rEP0_FIFO (*(volatile unsigned *)0x1520016C)
-#define rEP1_IN_CSR (*(volatile unsigned *)0x15200180)
-#define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184)
-#define rEP1_FIFO (*(volatile unsigned *)0x15200188)
-#define rEP2_IN_CSR (*(volatile unsigned *)0x15200190)
-#define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194)
-#define rEP2_FIFO (*(volatile unsigned *)0x15200198)
-#define rEP3_OUT_CSR (*(volatile unsigned *)0x152001A0)
-#define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001A4)
-#define rEP3_OUT_CNT (*(volatile unsigned *)0x152001A8)
-#define rEP3_FIFO (*(volatile unsigned *)0x152001AC)
-#define rEP4_OUT_CSR (*(volatile unsigned *)0x152001B0)
-#define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001B4)
-#define rEP4_OUT_CNT (*(volatile unsigned *)0x152001B8)
-#define rEP4_FIFO (*(volatile unsigned *)0x152001BC)
-#define rDMA_CON (*(volatile unsigned *)0x152001C0)
-#define rDMA_UNIT (*(volatile unsigned *)0x152001C4)
-#define rDMA_FIFO (*(volatile unsigned *)0x152001C8)
-#define rDMA_TX (*(volatile unsigned *)0x152001CC)
-#define rTEST_MODE (*(volatile unsigned *)0x152001F4)
-#define rIN_CON_REG (*(volatile unsigned *)0x152001F8)
-
-
-/* WATCH DOG TIMER */
-#define rWTCON (*(volatile unsigned *)0x15300000)
-#define rWTDAT (*(volatile unsigned *)0x15300004)
-#define rWTCNT (*(volatile unsigned *)0x15300008)
-
-
-/* IIC */
-#define rIICCON (*(volatile unsigned *)0x15400000)
-#define rIICSTAT (*(volatile unsigned *)0x15400004)
-#define rIICADD (*(volatile unsigned *)0x15400008)
-#define rIICDS (*(volatile unsigned *)0x1540000C)
-
-
-/* IIS */
-#define rIISCON (*(volatile unsigned *)0x15508000)
-#define rIISMOD (*(volatile unsigned *)0x15508004)
-#define rIISPSR (*(volatile unsigned *)0x15508008)
-#define rIISFIFCON (*(volatile unsigned *)0x1550800C)
-
-#ifdef __BIG_ENDIAN
-#define IISFIF ((volatile unsigned short *)0x15508012)
-
-#else /* Little Endian */
-#define IISFIF ((volatile unsigned short *)0x15508010)
-#endif
-
-
-/* I/O PORT */
-#define rPACON (*(volatile unsigned *)0x15600000)
-#define rPADAT (*(volatile unsigned *)0x15600004)
-
-#define rPBCON (*(volatile unsigned *)0x15600008)
-#define rPBDAT (*(volatile unsigned *)0x1560000C)
-#define rPBUP (*(volatile unsigned *)0x15600010)
-
-#define rPCCON (*(volatile unsigned *)0x15600014)
-#define rPCDAT (*(volatile unsigned *)0x15600018)
-#define rPCUP (*(volatile unsigned *)0x1560001C)
-
-#define rPDCON (*(volatile unsigned *)0x15600020)
-#define rPDDAT (*(volatile unsigned *)0x15600024)
-#define rPDUP (*(volatile unsigned *)0x15600028)
-
-#define rPECON (*(volatile unsigned *)0x1560002C)
-#define rPEDAT (*(volatile unsigned *)0x15600030)
-#define rPEUP (*(volatile unsigned *)0x15600034)
-
-#define rPFCON (*(volatile unsigned *)0x15600038)
-#define rPFDAT (*(volatile unsigned *)0x1560003C)
-#define rPFUP (*(volatile unsigned *)0x15600040)
-
-#define rPGCON (*(volatile unsigned *)0x15600044)
-#define rPGDAT (*(volatile unsigned *)0x15600048)
-#define rPGUP (*(volatile unsigned *)0x1560004C)
-
-#define rOPENCR (*(volatile unsigned *)0x15600050)
-#define rMISCCR (*(volatile unsigned *)0x15600054)
-#define rEXTINT (*(volatile unsigned *)0x15600058)
-
-
-/* RTC */
-#ifdef __BIG_ENDIAN
-#define rRTCCON (*(volatile unsigned char *)0x15700043)
-#define rRTCALM (*(volatile unsigned char *)0x15700053)
-#define rALMSEC (*(volatile unsigned char *)0x15700057)
-#define rALMMIN (*(volatile unsigned char *)0x1570005B)
-#define rALMHOUR (*(volatile unsigned char *)0x1570005F)
-#define rALMDAY (*(volatile unsigned char *)0x15700063)
-#define rALMMON (*(volatile unsigned char *)0x15700067)
-#define rALMYEAR (*(volatile unsigned char *)0x1570006B)
-#define rRTCRST (*(volatile unsigned char *)0x1570006F)
-#define rBCDSEC (*(volatile unsigned char *)0x15700073)
-#define rBCDMIN (*(volatile unsigned char *)0x15700077)
-#define rBCDHOUR (*(volatile unsigned char *)0x1570007B)
-#define rBCDDAY (*(volatile unsigned char *)0x1570007F)
-#define rBCDDATE (*(volatile unsigned char *)0x15700083)
-#define rBCDMON (*(volatile unsigned char *)0x15700087)
-#define rBCDYEAR (*(volatile unsigned char *)0x1570008B)
-#define rTICINT (*(volatile unsigned char *)0x15700047)
-
-#else /* Little Endian */
-#define rRTCCON (*(volatile unsigned char *)0x15700040)
-#define rRTCALM (*(volatile unsigned char *)0x15700050)
-#define rALMSEC (*(volatile unsigned char *)0x15700054)
-#define rALMMIN (*(volatile unsigned char *)0x15700058)
-#define rALMHOUR (*(volatile unsigned char *)0x1570005C)
-#define rALMDAY (*(volatile unsigned char *)0x15700060)
-#define rALMMON (*(volatile unsigned char *)0x15700064)
-#define rALMYEAR (*(volatile unsigned char *)0x15700068)
-#define rRTCRST (*(volatile unsigned char *)0x1570006C)
-#define rBCDSEC (*(volatile unsigned char *)0x15700070)
-#define rBCDMIN (*(volatile unsigned char *)0x15700074)
-#define rBCDHOUR (*(volatile unsigned char *)0x15700078)
-#define rBCDDAY (*(volatile unsigned char *)0x1570007C)
-#define rBCDDATE (*(volatile unsigned char *)0x15700080)
-#define rBCDMON (*(volatile unsigned char *)0x15700084)
-#define rBCDYEAR (*(volatile unsigned char *)0x15700088)
-#define rTICINT (*(volatile unsigned char *)0x15700044)
-#endif
-
-
-/* ADC */
-#define rADCCON (*(volatile unsigned *)0x15800000)
-#define rADCDAT (*(volatile unsigned *)0x15800004)
-
-
-/* SPI */
-#define rSPCON (*(volatile unsigned *)0x15900000)
-#define rSPSTA (*(volatile unsigned *)0x15900004)
-#define rSPPIN (*(volatile unsigned *)0x15900008)
-#define rSPPRE (*(volatile unsigned *)0x1590000C)
-#define rSPTDAT (*(volatile unsigned *)0x15900010)
-#define rSPRDAT (*(volatile unsigned *)0x15900014)
-
-
-/* MMC INTERFACE */
-#define rMMCON (*(volatile unsigned *)0x15a00000)
-#define rMMCRR (*(volatile unsigned *)0x15a00004)
-#define rMMFCON (*(volatile unsigned *)0x15a00008)
-#define rMMSTA (*(volatile unsigned *)0x15a0000C)
-#define rMMFSTA (*(volatile unsigned *)0x15a00010)
-#define rMMPRE (*(volatile unsigned *)0x15a00014)
-#define rMMLEN (*(volatile unsigned *)0x15a00018)
-#define rMMCR7 (*(volatile unsigned *)0x15a0001C)
-#define rMMRSP0 (*(volatile unsigned *)0x15a00020)
-#define rMMRSP1 (*(volatile unsigned *)0x15a00024)
-#define rMMRSP2 (*(volatile unsigned *)0x15a00028)
-#define rMMRSP3 (*(volatile unsigned *)0x15a0002C)
-#define rMMCMD0 (*(volatile unsigned *)0x15a00030)
-#define rMMCMD1 (*(volatile unsigned *)0x15a00034)
-#define rMMCR16 (*(volatile unsigned *)0x15a00038)
-#define rMMDAT (*(volatile unsigned *)0x15a0003C)
-
/* ISR */
#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
@@ -550,5 +217,4 @@ static inline S3C2400_MMC * S3C2400_GetBase_MMC(void)
rINTPND;\
}
/* Wait until rINTPND is changed for the case that the ISR is very short. */
-#endif
#endif /*__S3C2400_H__*/
diff --git a/include/s3c2410.h b/include/s3c2410.h
index 87135b4..f5a21c7 100644
--- a/include/s3c2410.h
+++ b/include/s3c2410.h
@@ -68,76 +68,75 @@ typedef enum {
/* include common stuff */
#include <s3c24x0.h>
-
-static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
+static inline S3C24X0_MEMCTL *S3C24X0_GetBase_MEMCTL(void)
{
return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
}
-static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
+static inline S3C24X0_USB_HOST *S3C24X0_GetBase_USB_HOST(void)
{
return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
}
-static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
+static inline S3C24X0_INTERRUPT *S3C24X0_GetBase_INTERRUPT(void)
{
return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
}
-static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
+static inline S3C24X0_DMAS *S3C24X0_GetBase_DMAS(void)
{
return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
}
-static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
+static inline S3C24X0_CLOCK_POWER *S3C24X0_GetBase_CLOCK_POWER(void)
{
return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
}
-static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
+static inline S3C24X0_LCD *S3C24X0_GetBase_LCD(void)
{
return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
}
-static inline S3C2410_NAND * S3C2410_GetBase_NAND(void)
+static inline S3C2410_NAND *S3C2410_GetBase_NAND(void)
{
return (S3C2410_NAND * const)S3C2410_NAND_BASE;
}
-static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+static inline S3C24X0_UART *S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
{
return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
}
-static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
+static inline S3C24X0_TIMERS *S3C24X0_GetBase_TIMERS(void)
{
return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
}
-static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
+static inline S3C24X0_USB_DEVICE *S3C24X0_GetBase_USB_DEVICE(void)
{
return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
}
-static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
+static inline S3C24X0_WATCHDOG *S3C24X0_GetBase_WATCHDOG(void)
{
return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
}
-static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
+static inline S3C24X0_I2C *S3C24X0_GetBase_I2C(void)
{
return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
}
-static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
+static inline S3C24X0_I2S *S3C24X0_GetBase_I2S(void)
{
return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
}
-static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
+static inline S3C24X0_GPIO *S3C24X0_GetBase_GPIO(void)
{
return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
}
-static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
+static inline S3C24X0_RTC *S3C24X0_GetBase_RTC(void)
{
return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
}
-static inline S3C2410_ADC * S3C2410_GetBase_ADC(void)
+static inline S3C2410_ADC *S3C2410_GetBase_ADC(void)
{
return (S3C2410_ADC * const)S3C2410_ADC_BASE;
}
-static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
+static inline S3C24X0_SPI *S3C24X0_GetBase_SPI(void)
{
return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
}
-static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
+static inline S3C2410_SDI *S3C2410_GetBase_SDI(void)
{
return (S3C2410_SDI * const)S3C2410_SDI_BASE;
}
diff --git a/include/s3c24x0.h b/include/s3c24x0.h
index 71f35a5..da984c0 100644
--- a/include/s3c24x0.h
+++ b/include/s3c24x0.h
@@ -31,337 +31,325 @@
#ifndef __S3C24X0_H__
#define __S3C24X0_H__
-typedef volatile u8 S3C24X0_REG8;
-typedef volatile u16 S3C24X0_REG16;
-typedef volatile u32 S3C24X0_REG32;
+typedef volatile u8 S3C24X0_REG8;
+typedef volatile u16 S3C24X0_REG16;
+typedef volatile u32 S3C24X0_REG32;
/* Memory controller (see manual chapter 5) */
typedef struct {
- S3C24X0_REG32 BWSCON;
- S3C24X0_REG32 BANKCON[8];
- S3C24X0_REG32 REFRESH;
- S3C24X0_REG32 BANKSIZE;
- S3C24X0_REG32 MRSRB6;
- S3C24X0_REG32 MRSRB7;
+ S3C24X0_REG32 BWSCON;
+ S3C24X0_REG32 BANKCON[8];
+ S3C24X0_REG32 REFRESH;
+ S3C24X0_REG32 BANKSIZE;
+ S3C24X0_REG32 MRSRB6;
+ S3C24X0_REG32 MRSRB7;
} /*__attribute__((__packed__))*/ S3C24X0_MEMCTL;
-
/* USB HOST (see manual chapter 12) */
typedef struct {
- S3C24X0_REG32 HcRevision;
- S3C24X0_REG32 HcControl;
- S3C24X0_REG32 HcCommonStatus;
- S3C24X0_REG32 HcInterruptStatus;
- S3C24X0_REG32 HcInterruptEnable;
- S3C24X0_REG32 HcInterruptDisable;
- S3C24X0_REG32 HcHCCA;
- S3C24X0_REG32 HcPeriodCuttendED;
- S3C24X0_REG32 HcControlHeadED;
- S3C24X0_REG32 HcControlCurrentED;
- S3C24X0_REG32 HcBulkHeadED;
- S3C24X0_REG32 HcBuldCurrentED;
- S3C24X0_REG32 HcDoneHead;
- S3C24X0_REG32 HcRmInterval;
- S3C24X0_REG32 HcFmRemaining;
- S3C24X0_REG32 HcFmNumber;
- S3C24X0_REG32 HcPeriodicStart;
- S3C24X0_REG32 HcLSThreshold;
- S3C24X0_REG32 HcRhDescriptorA;
- S3C24X0_REG32 HcRhDescriptorB;
- S3C24X0_REG32 HcRhStatus;
- S3C24X0_REG32 HcRhPortStatus1;
- S3C24X0_REG32 HcRhPortStatus2;
+ S3C24X0_REG32 HcRevision;
+ S3C24X0_REG32 HcControl;
+ S3C24X0_REG32 HcCommonStatus;
+ S3C24X0_REG32 HcInterruptStatus;
+ S3C24X0_REG32 HcInterruptEnable;
+ S3C24X0_REG32 HcInterruptDisable;
+ S3C24X0_REG32 HcHCCA;
+ S3C24X0_REG32 HcPeriodCuttendED;
+ S3C24X0_REG32 HcControlHeadED;
+ S3C24X0_REG32 HcControlCurrentED;
+ S3C24X0_REG32 HcBulkHeadED;
+ S3C24X0_REG32 HcBuldCurrentED;
+ S3C24X0_REG32 HcDoneHead;
+ S3C24X0_REG32 HcRmInterval;
+ S3C24X0_REG32 HcFmRemaining;
+ S3C24X0_REG32 HcFmNumber;
+ S3C24X0_REG32 HcPeriodicStart;
+ S3C24X0_REG32 HcLSThreshold;
+ S3C24X0_REG32 HcRhDescriptorA;
+ S3C24X0_REG32 HcRhDescriptorB;
+ S3C24X0_REG32 HcRhStatus;
+ S3C24X0_REG32 HcRhPortStatus1;
+ S3C24X0_REG32 HcRhPortStatus2;
} /*__attribute__((__packed__))*/ S3C24X0_USB_HOST;
-
/* INTERRUPT (see manual chapter 14) */
typedef struct {
- S3C24X0_REG32 SRCPND;
- S3C24X0_REG32 INTMOD;
- S3C24X0_REG32 INTMSK;
- S3C24X0_REG32 PRIORITY;
- S3C24X0_REG32 INTPND;
- S3C24X0_REG32 INTOFFSET;
+ S3C24X0_REG32 SRCPND;
+ S3C24X0_REG32 INTMOD;
+ S3C24X0_REG32 INTMSK;
+ S3C24X0_REG32 PRIORITY;
+ S3C24X0_REG32 INTPND;
+ S3C24X0_REG32 INTOFFSET;
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 SUBSRCPND;
- S3C24X0_REG32 INTSUBMSK;
+ S3C24X0_REG32 SUBSRCPND;
+ S3C24X0_REG32 INTSUBMSK;
#endif
} /*__attribute__((__packed__))*/ S3C24X0_INTERRUPT;
-
/* DMAS (see manual chapter 8) */
typedef struct {
- S3C24X0_REG32 DISRC;
+ S3C24X0_REG32 DISRC;
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DISRCC;
+ S3C24X0_REG32 DISRCC;
#endif
- S3C24X0_REG32 DIDST;
+ S3C24X0_REG32 DIDST;
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DIDSTC;
+ S3C24X0_REG32 DIDSTC;
#endif
- S3C24X0_REG32 DCON;
- S3C24X0_REG32 DSTAT;
- S3C24X0_REG32 DCSRC;
- S3C24X0_REG32 DCDST;
- S3C24X0_REG32 DMASKTRIG;
+ S3C24X0_REG32 DCON;
+ S3C24X0_REG32 DSTAT;
+ S3C24X0_REG32 DCSRC;
+ S3C24X0_REG32 DCDST;
+ S3C24X0_REG32 DMASKTRIG;
#ifdef CONFIG_S3C2400
- S3C24X0_REG32 res[1];
+ S3C24X0_REG32 res[1];
#endif
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 res[7];
+ S3C24X0_REG32 res[7];
#endif
} /*__attribute__((__packed__))*/ S3C24X0_DMA;
typedef struct {
- S3C24X0_DMA dma[4];
+ S3C24X0_DMA dma[4];
} /*__attribute__((__packed__))*/ S3C24X0_DMAS;
-
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/* (see S3C2410 manual chapter 7) */
typedef struct {
- S3C24X0_REG32 LOCKTIME;
- S3C24X0_REG32 MPLLCON;
- S3C24X0_REG32 UPLLCON;
- S3C24X0_REG32 CLKCON;
- S3C24X0_REG32 CLKSLOW;
- S3C24X0_REG32 CLKDIVN;
+ S3C24X0_REG32 LOCKTIME;
+ S3C24X0_REG32 MPLLCON;
+ S3C24X0_REG32 UPLLCON;
+ S3C24X0_REG32 CLKCON;
+ S3C24X0_REG32 CLKSLOW;
+ S3C24X0_REG32 CLKDIVN;
} /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
-
/* LCD CONTROLLER (see manual chapter 15) */
typedef struct {
- S3C24X0_REG32 LCDCON1;
- S3C24X0_REG32 LCDCON2;
- S3C24X0_REG32 LCDCON3;
- S3C24X0_REG32 LCDCON4;
- S3C24X0_REG32 LCDCON5;
- S3C24X0_REG32 LCDSADDR1;
- S3C24X0_REG32 LCDSADDR2;
- S3C24X0_REG32 LCDSADDR3;
- S3C24X0_REG32 REDLUT;
- S3C24X0_REG32 GREENLUT;
- S3C24X0_REG32 BLUELUT;
- S3C24X0_REG32 res[8];
- S3C24X0_REG32 DITHMODE;
- S3C24X0_REG32 TPAL;
+ S3C24X0_REG32 LCDCON1;
+ S3C24X0_REG32 LCDCON2;
+ S3C24X0_REG32 LCDCON3;
+ S3C24X0_REG32 LCDCON4;
+ S3C24X0_REG32 LCDCON5;
+ S3C24X0_REG32 LCDSADDR1;
+ S3C24X0_REG32 LCDSADDR2;
+ S3C24X0_REG32 LCDSADDR3;
+ S3C24X0_REG32 REDLUT;
+ S3C24X0_REG32 GREENLUT;
+ S3C24X0_REG32 BLUELUT;
+ S3C24X0_REG32 res[8];
+ S3C24X0_REG32 DITHMODE;
+ S3C24X0_REG32 TPAL;
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 LCDINTPND;
- S3C24X0_REG32 LCDSRCPND;
- S3C24X0_REG32 LCDINTMSK;
- S3C24X0_REG32 LPCSEL;
+ S3C24X0_REG32 LCDINTPND;
+ S3C24X0_REG32 LCDSRCPND;
+ S3C24X0_REG32 LCDINTMSK;
+ S3C24X0_REG32 LPCSEL;
#endif
} /*__attribute__((__packed__))*/ S3C24X0_LCD;
-
/* NAND FLASH (see S3C2410 manual chapter 6) */
typedef struct {
- S3C24X0_REG32 NFCONF;
- S3C24X0_REG32 NFCMD;
- S3C24X0_REG32 NFADDR;
- S3C24X0_REG32 NFDATA;
- S3C24X0_REG32 NFSTAT;
- S3C24X0_REG32 NFECC;
+ S3C24X0_REG32 NFCONF;
+ S3C24X0_REG32 NFCMD;
+ S3C24X0_REG32 NFADDR;
+ S3C24X0_REG32 NFDATA;
+ S3C24X0_REG32 NFSTAT;
+ S3C24X0_REG32 NFECC;
} /*__attribute__((__packed__))*/ S3C2410_NAND;
-
/* UART (see manual chapter 11) */
typedef struct {
- S3C24X0_REG32 ULCON;
- S3C24X0_REG32 UCON;
- S3C24X0_REG32 UFCON;
- S3C24X0_REG32 UMCON;
- S3C24X0_REG32 UTRSTAT;
- S3C24X0_REG32 UERSTAT;
- S3C24X0_REG32 UFSTAT;
- S3C24X0_REG32 UMSTAT;
+ S3C24X0_REG32 ULCON;
+ S3C24X0_REG32 UCON;
+ S3C24X0_REG32 UFCON;
+ S3C24X0_REG32 UMCON;
+ S3C24X0_REG32 UTRSTAT;
+ S3C24X0_REG32 UERSTAT;
+ S3C24X0_REG32 UFSTAT;
+ S3C24X0_REG32 UMSTAT;
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 URXH;
-#else /* Little Endian */
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 URXH;
- S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 UTXH;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 URXH;
+#else /* Little Endian */
+ S3C24X0_REG8 UTXH;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 URXH;
+ S3C24X0_REG8 res2[3];
#endif
- S3C24X0_REG32 UBRDIV;
+ S3C24X0_REG32 UBRDIV;
} /*__attribute__((__packed__))*/ S3C24X0_UART;
-
/* PWM TIMER (see manual chapter 10) */
typedef struct {
- S3C24X0_REG32 TCNTB;
- S3C24X0_REG32 TCMPB;
- S3C24X0_REG32 TCNTO;
+ S3C24X0_REG32 TCNTB;
+ S3C24X0_REG32 TCMPB;
+ S3C24X0_REG32 TCNTO;
} /*__attribute__((__packed__))*/ S3C24X0_TIMER;
typedef struct {
- S3C24X0_REG32 TCFG0;
- S3C24X0_REG32 TCFG1;
- S3C24X0_REG32 TCON;
- S3C24X0_TIMER ch[4];
- S3C24X0_REG32 TCNTB4;
- S3C24X0_REG32 TCNTO4;
+ S3C24X0_REG32 TCFG0;
+ S3C24X0_REG32 TCFG1;
+ S3C24X0_REG32 TCON;
+ S3C24X0_TIMER ch[4];
+ S3C24X0_REG32 TCNTB4;
+ S3C24X0_REG32 TCNTO4;
} /*__attribute__((__packed__))*/ S3C24X0_TIMERS;
-
/* USB DEVICE (see manual chapter 13) */
typedef struct {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 EP_FIFO_REG;
-#else /* little endian */
- S3C24X0_REG8 EP_FIFO_REG;
- S3C24X0_REG8 res[3];
+ S3C24X0_REG8 res[3];
+ S3C24X0_REG8 EP_FIFO_REG;
+#else /* little endian */
+ S3C24X0_REG8 EP_FIFO_REG;
+ S3C24X0_REG8 res[3];
#endif
} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_FIFOS;
typedef struct {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
-#else /* little endian */
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
- S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 EP_DMA_CON;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 EP_DMA_UNIT;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 EP_DMA_FIFO;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 EP_DMA_TTC_L;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 EP_DMA_TTC_M;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 EP_DMA_TTC_H;
+#else /* little endian */
+ S3C24X0_REG8 EP_DMA_CON;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 EP_DMA_UNIT;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 EP_DMA_FIFO;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 EP_DMA_TTC_L;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 EP_DMA_TTC_M;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 EP_DMA_TTC_H;
+ S3C24X0_REG8 res6[3];
#endif
} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS;
typedef struct {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res4[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res6[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
-#else /* little endian */
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res3[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res5[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res9[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
- S3C24X0_REG8 res16[3];
-#endif /* __BIG_ENDIAN */
- S3C24X0_USB_DEV_FIFOS fifo[5];
- S3C24X0_USB_DEV_DMAS dma[5];
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 FUNC_ADDR_REG;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 PWR_REG;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 EP_INT_REG;
+ S3C24X0_REG8 res4[15];
+ S3C24X0_REG8 USB_INT_REG;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 EP_INT_EN_REG;
+ S3C24X0_REG8 res6[15];
+ S3C24X0_REG8 USB_INT_EN_REG;
+ S3C24X0_REG8 res7[3];
+ S3C24X0_REG8 FRAME_NUM1_REG;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 FRAME_NUM2_REG;
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG8 INDEX_REG;
+ S3C24X0_REG8 res10[7];
+ S3C24X0_REG8 MAXP_REG;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
+ S3C24X0_REG8 res12[3];
+ S3C24X0_REG8 IN_CSR2_REG;
+ S3C24X0_REG8 res13[7];
+ S3C24X0_REG8 OUT_CSR1_REG;
+ S3C24X0_REG8 res14[3];
+ S3C24X0_REG8 OUT_CSR2_REG;
+ S3C24X0_REG8 res15[3];
+ S3C24X0_REG8 OUT_FIFO_CNT1_REG;
+ S3C24X0_REG8 res16[3];
+ S3C24X0_REG8 OUT_FIFO_CNT2_REG;
+#else /* little endian */
+ S3C24X0_REG8 FUNC_ADDR_REG;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 PWR_REG;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 EP_INT_REG;
+ S3C24X0_REG8 res3[15];
+ S3C24X0_REG8 USB_INT_REG;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 EP_INT_EN_REG;
+ S3C24X0_REG8 res5[15];
+ S3C24X0_REG8 USB_INT_EN_REG;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 FRAME_NUM1_REG;
+ S3C24X0_REG8 res7[3];
+ S3C24X0_REG8 FRAME_NUM2_REG;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 INDEX_REG;
+ S3C24X0_REG8 res9[7];
+ S3C24X0_REG8 MAXP_REG;
+ S3C24X0_REG8 res10[7];
+ S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 IN_CSR2_REG;
+ S3C24X0_REG8 res12[3];
+ S3C24X0_REG8 OUT_CSR1_REG;
+ S3C24X0_REG8 res13[7];
+ S3C24X0_REG8 OUT_CSR2_REG;
+ S3C24X0_REG8 res14[3];
+ S3C24X0_REG8 OUT_FIFO_CNT1_REG;
+ S3C24X0_REG8 res15[3];
+ S3C24X0_REG8 OUT_FIFO_CNT2_REG;
+ S3C24X0_REG8 res16[3];
+#endif /* __BIG_ENDIAN */
+ S3C24X0_USB_DEV_FIFOS fifo[5];
+ S3C24X0_USB_DEV_DMAS dma[5];
} /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
-
/* WATCH DOG TIMER (see manual chapter 18) */
typedef struct {
- S3C24X0_REG32 WTCON;
- S3C24X0_REG32 WTDAT;
- S3C24X0_REG32 WTCNT;
+ S3C24X0_REG32 WTCON;
+ S3C24X0_REG32 WTDAT;
+ S3C24X0_REG32 WTCNT;
} /*__attribute__((__packed__))*/ S3C24X0_WATCHDOG;
-
/* IIC (see manual chapter 20) */
typedef struct {
- S3C24X0_REG32 IICCON;
- S3C24X0_REG32 IICSTAT;
- S3C24X0_REG32 IICADD;
- S3C24X0_REG32 IICDS;
+ S3C24X0_REG32 IICCON;
+ S3C24X0_REG32 IICSTAT;
+ S3C24X0_REG32 IICADD;
+ S3C24X0_REG32 IICDS;
} /*__attribute__((__packed__))*/ S3C24X0_I2C;
-
/* IIS (see manual chapter 21) */
typedef struct {
#ifdef __BIG_ENDIAN
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 IISFIFO;
-#else /* little endian */
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFIFO;
- S3C24X0_REG16 res5;
+ S3C24X0_REG16 res1;
+ S3C24X0_REG16 IISCON;
+ S3C24X0_REG16 res2;
+ S3C24X0_REG16 IISMOD;
+ S3C24X0_REG16 res3;
+ S3C24X0_REG16 IISPSR;
+ S3C24X0_REG16 res4;
+ S3C24X0_REG16 IISFCON;
+ S3C24X0_REG16 res5;
+ S3C24X0_REG16 IISFIFO;
+#else /* little endian */
+ S3C24X0_REG16 IISCON;
+ S3C24X0_REG16 res1;
+ S3C24X0_REG16 IISMOD;
+ S3C24X0_REG16 res2;
+ S3C24X0_REG16 IISPSR;
+ S3C24X0_REG16 res3;
+ S3C24X0_REG16 IISFCON;
+ S3C24X0_REG16 res4;
+ S3C24X0_REG16 IISFIFO;
+ S3C24X0_REG16 res5;
#endif
} /*__attribute__((__packed__))*/ S3C24X0_I2S;
@@ -369,87 +357,87 @@ typedef struct {
/* I/O PORT (see manual chapter 9) */
typedef struct {
#ifdef CONFIG_S3C2400
- S3C24X0_REG32 PACON;
- S3C24X0_REG32 PADAT;
+ S3C24X0_REG32 PACON;
+ S3C24X0_REG32 PADAT;
- S3C24X0_REG32 PBCON;
- S3C24X0_REG32 PBDAT;
- S3C24X0_REG32 PBUP;
+ S3C24X0_REG32 PBCON;
+ S3C24X0_REG32 PBDAT;
+ S3C24X0_REG32 PBUP;
- S3C24X0_REG32 PCCON;
- S3C24X0_REG32 PCDAT;
- S3C24X0_REG32 PCUP;
+ S3C24X0_REG32 PCCON;
+ S3C24X0_REG32 PCDAT;
+ S3C24X0_REG32 PCUP;
- S3C24X0_REG32 PDCON;
- S3C24X0_REG32 PDDAT;
- S3C24X0_REG32 PDUP;
+ S3C24X0_REG32 PDCON;
+ S3C24X0_REG32 PDDAT;
+ S3C24X0_REG32 PDUP;
- S3C24X0_REG32 PECON;
- S3C24X0_REG32 PEDAT;
- S3C24X0_REG32 PEUP;
+ S3C24X0_REG32 PECON;
+ S3C24X0_REG32 PEDAT;
+ S3C24X0_REG32 PEUP;
- S3C24X0_REG32 PFCON;
- S3C24X0_REG32 PFDAT;
- S3C24X0_REG32 PFUP;
+ S3C24X0_REG32 PFCON;
+ S3C24X0_REG32 PFDAT;
+ S3C24X0_REG32 PFUP;
- S3C24X0_REG32 PGCON;
- S3C24X0_REG32 PGDAT;
- S3C24X0_REG32 PGUP;
+ S3C24X0_REG32 PGCON;
+ S3C24X0_REG32 PGDAT;
+ S3C24X0_REG32 PGUP;
- S3C24X0_REG32 OPENCR;
+ S3C24X0_REG32 OPENCR;
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 EXTINT;
+ S3C24X0_REG32 MISCCR;
+ S3C24X0_REG32 EXTINT;
#endif
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 GPACON;
- S3C24X0_REG32 GPADAT;
- S3C24X0_REG32 res1[2];
- S3C24X0_REG32 GPBCON;
- S3C24X0_REG32 GPBDAT;
- S3C24X0_REG32 GPBUP;
- S3C24X0_REG32 res2;
- S3C24X0_REG32 GPCCON;
- S3C24X0_REG32 GPCDAT;
- S3C24X0_REG32 GPCUP;
- S3C24X0_REG32 res3;
- S3C24X0_REG32 GPDCON;
- S3C24X0_REG32 GPDDAT;
- S3C24X0_REG32 GPDUP;
- S3C24X0_REG32 res4;
- S3C24X0_REG32 GPECON;
- S3C24X0_REG32 GPEDAT;
- S3C24X0_REG32 GPEUP;
- S3C24X0_REG32 res5;
- S3C24X0_REG32 GPFCON;
- S3C24X0_REG32 GPFDAT;
- S3C24X0_REG32 GPFUP;
- S3C24X0_REG32 res6;
- S3C24X0_REG32 GPGCON;
- S3C24X0_REG32 GPGDAT;
- S3C24X0_REG32 GPGUP;
- S3C24X0_REG32 res7;
- S3C24X0_REG32 GPHCON;
- S3C24X0_REG32 GPHDAT;
- S3C24X0_REG32 GPHUP;
- S3C24X0_REG32 res8;
-
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 DCLKCON;
- S3C24X0_REG32 EXTINT0;
- S3C24X0_REG32 EXTINT1;
- S3C24X0_REG32 EXTINT2;
- S3C24X0_REG32 EINTFLT0;
- S3C24X0_REG32 EINTFLT1;
- S3C24X0_REG32 EINTFLT2;
- S3C24X0_REG32 EINTFLT3;
- S3C24X0_REG32 EINTMASK;
- S3C24X0_REG32 EINTPEND;
- S3C24X0_REG32 GSTATUS0;
- S3C24X0_REG32 GSTATUS1;
- S3C24X0_REG32 GSTATUS2;
- S3C24X0_REG32 GSTATUS3;
- S3C24X0_REG32 GSTATUS4;
+ S3C24X0_REG32 GPACON;
+ S3C24X0_REG32 GPADAT;
+ S3C24X0_REG32 res1[2];
+ S3C24X0_REG32 GPBCON;
+ S3C24X0_REG32 GPBDAT;
+ S3C24X0_REG32 GPBUP;
+ S3C24X0_REG32 res2;
+ S3C24X0_REG32 GPCCON;
+ S3C24X0_REG32 GPCDAT;
+ S3C24X0_REG32 GPCUP;
+ S3C24X0_REG32 res3;
+ S3C24X0_REG32 GPDCON;
+ S3C24X0_REG32 GPDDAT;
+ S3C24X0_REG32 GPDUP;
+ S3C24X0_REG32 res4;
+ S3C24X0_REG32 GPECON;
+ S3C24X0_REG32 GPEDAT;
+ S3C24X0_REG32 GPEUP;
+ S3C24X0_REG32 res5;
+ S3C24X0_REG32 GPFCON;
+ S3C24X0_REG32 GPFDAT;
+ S3C24X0_REG32 GPFUP;
+ S3C24X0_REG32 res6;
+ S3C24X0_REG32 GPGCON;
+ S3C24X0_REG32 GPGDAT;
+ S3C24X0_REG32 GPGUP;
+ S3C24X0_REG32 res7;
+ S3C24X0_REG32 GPHCON;
+ S3C24X0_REG32 GPHDAT;
+ S3C24X0_REG32 GPHUP;
+ S3C24X0_REG32 res8;
+
+ S3C24X0_REG32 MISCCR;
+ S3C24X0_REG32 DCLKCON;
+ S3C24X0_REG32 EXTINT0;
+ S3C24X0_REG32 EXTINT1;
+ S3C24X0_REG32 EXTINT2;
+ S3C24X0_REG32 EINTFLT0;
+ S3C24X0_REG32 EINTFLT1;
+ S3C24X0_REG32 EINTFLT2;
+ S3C24X0_REG32 EINTFLT3;
+ S3C24X0_REG32 EINTMASK;
+ S3C24X0_REG32 EINTPEND;
+ S3C24X0_REG32 GSTATUS0;
+ S3C24X0_REG32 GSTATUS1;
+ S3C24X0_REG32 GSTATUS2;
+ S3C24X0_REG32 GSTATUS3;
+ S3C24X0_REG32 GSTATUS4;
#endif
} /*__attribute__((__packed__))*/ S3C24X0_GPIO;
@@ -457,679 +445,189 @@ typedef struct {
/* RTC (see manual chapter 17) */
typedef struct {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[67];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res3[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res17[3];
- S3C24X0_REG8 BCDYEAR;
-#else /* little endian */
- S3C24X0_REG8 res0[64];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res2[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDYEAR;
- S3C24X0_REG8 res17[3];
+ S3C24X0_REG8 res1[67];
+ S3C24X0_REG8 RTCCON;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 TICNT;
+ S3C24X0_REG8 res3[11];
+ S3C24X0_REG8 RTCALM;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 ALMSEC;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 ALMMIN;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 ALMHOUR;
+ S3C24X0_REG8 res7[3];
+ S3C24X0_REG8 ALMDATE;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 ALMMON;
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG8 ALMYEAR;
+ S3C24X0_REG8 res10[3];
+ S3C24X0_REG8 RTCRST;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 BCDSEC;
+ S3C24X0_REG8 res12[3];
+ S3C24X0_REG8 BCDMIN;
+ S3C24X0_REG8 res13[3];
+ S3C24X0_REG8 BCDHOUR;
+ S3C24X0_REG8 res14[3];
+ S3C24X0_REG8 BCDDATE;
+ S3C24X0_REG8 res15[3];
+ S3C24X0_REG8 BCDDAY;
+ S3C24X0_REG8 res16[3];
+ S3C24X0_REG8 BCDMON;
+ S3C24X0_REG8 res17[3];
+ S3C24X0_REG8 BCDYEAR;
+#else /* little endian */
+ S3C24X0_REG8 res0[64];
+ S3C24X0_REG8 RTCCON;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 TICNT;
+ S3C24X0_REG8 res2[11];
+ S3C24X0_REG8 RTCALM;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 ALMSEC;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 ALMMIN;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 ALMHOUR;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 ALMDATE;
+ S3C24X0_REG8 res7[3];
+ S3C24X0_REG8 ALMMON;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 ALMYEAR;
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG8 RTCRST;
+ S3C24X0_REG8 res10[3];
+ S3C24X0_REG8 BCDSEC;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 BCDMIN;
+ S3C24X0_REG8 res12[3];
+ S3C24X0_REG8 BCDHOUR;
+ S3C24X0_REG8 res13[3];
+ S3C24X0_REG8 BCDDATE;
+ S3C24X0_REG8 res14[3];
+ S3C24X0_REG8 BCDDAY;
+ S3C24X0_REG8 res15[3];
+ S3C24X0_REG8 BCDMON;
+ S3C24X0_REG8 res16[3];
+ S3C24X0_REG8 BCDYEAR;
+ S3C24X0_REG8 res17[3];
#endif
} /*__attribute__((__packed__))*/ S3C24X0_RTC;
-
/* ADC (see manual chapter 16) */
typedef struct {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCDAT;
+ S3C24X0_REG32 ADCCON;
+ S3C24X0_REG32 ADCDAT;
} /*__attribute__((__packed__))*/ S3C2400_ADC;
-
/* ADC (see manual chapter 16) */
typedef struct {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCTSC;
- S3C24X0_REG32 ADCDLY;
- S3C24X0_REG32 ADCDAT0;
- S3C24X0_REG32 ADCDAT1;
+ S3C24X0_REG32 ADCCON;
+ S3C24X0_REG32 ADCTSC;
+ S3C24X0_REG32 ADCDLY;
+ S3C24X0_REG32 ADCDAT0;
+ S3C24X0_REG32 ADCDAT1;
} /*__attribute__((__packed__))*/ S3C2410_ADC;
-
/* SPI (see manual chapter 22) */
typedef struct {
- S3C24X0_REG32 SPCON;
- S3C24X0_REG32 SPSTA;
- S3C24X0_REG32 SPPIN;
- S3C24X0_REG32 SPPRE;
- S3C24X0_REG32 SPTDAT;
- S3C24X0_REG32 SPRDAT;
- S3C24X0_REG32 res[2];
-} __attribute__((__packed__)) S3C24X0_SPI_CHANNEL;
+ S3C24X0_REG32 SPCON;
+ S3C24X0_REG32 SPSTA;
+ S3C24X0_REG32 SPPIN;
+ S3C24X0_REG32 SPPRE;
+ S3C24X0_REG32 SPTDAT;
+ S3C24X0_REG32 SPRDAT;
+ S3C24X0_REG32 res[2];
+} __attribute__ ((__packed__)) S3C24X0_SPI_CHANNEL;
typedef struct {
- S3C24X0_SPI_CHANNEL ch[S3C24X0_SPI_CHANNELS];
+ S3C24X0_SPI_CHANNEL ch[S3C24X0_SPI_CHANNELS];
} /*__attribute__((__packed__))*/ S3C24X0_SPI;
-
/* MMC INTERFACE (see S3C2400 manual chapter 19) */
typedef struct {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG16 res7;
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 res10;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 MMDAT;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 MMCON;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 MMCRR;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 MMFCON;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 MMSTA;
+ S3C24X0_REG16 res5;
+ S3C24X0_REG16 MMFSTA;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 MMPRE;
+ S3C24X0_REG16 res7;
+ S3C24X0_REG16 MMLEN;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 MMCR7;
+ S3C24X0_REG32 MMRSP[4];
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG8 MMCMD0;
+ S3C24X0_REG32 MMCMD1;
+ S3C24X0_REG16 res10;
+ S3C24X0_REG16 MMCR16;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 MMDAT;
#else
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG16 res7;
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG16 res10;
- S3C24X0_REG8 MMDAT;
- S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 MMCON;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 MMCRR;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 MMFCON;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 MMSTA;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG16 MMFSTA;
+ S3C24X0_REG16 res5;
+ S3C24X0_REG8 MMPRE;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG16 MMLEN;
+ S3C24X0_REG16 res7;
+ S3C24X0_REG8 MMCR7;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG32 MMRSP[4];
+ S3C24X0_REG8 MMCMD0;
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG32 MMCMD1;
+ S3C24X0_REG16 MMCR16;
+ S3C24X0_REG16 res10;
+ S3C24X0_REG8 MMDAT;
+ S3C24X0_REG8 res11[3];
#endif
} /*__attribute__((__packed__))*/ S3C2400_MMC;
-
/* SD INTERFACE (see S3C2410 manual chapter 19) */
typedef struct {
- S3C24X0_REG32 SDICON;
- S3C24X0_REG32 SDIPRE;
- S3C24X0_REG32 SDICARG;
- S3C24X0_REG32 SDICCON;
- S3C24X0_REG32 SDICSTA;
- S3C24X0_REG32 SDIRSP0;
- S3C24X0_REG32 SDIRSP1;
- S3C24X0_REG32 SDIRSP2;
- S3C24X0_REG32 SDIRSP3;
- S3C24X0_REG32 SDIDTIMER;
- S3C24X0_REG32 SDIBSIZE;
- S3C24X0_REG32 SDIDCON;
- S3C24X0_REG32 SDIDCNT;
- S3C24X0_REG32 SDIDSTA;
- S3C24X0_REG32 SDIFSTA;
+ S3C24X0_REG32 SDICON;
+ S3C24X0_REG32 SDIPRE;
+ S3C24X0_REG32 SDICARG;
+ S3C24X0_REG32 SDICCON;
+ S3C24X0_REG32 SDICSTA;
+ S3C24X0_REG32 SDIRSP0;
+ S3C24X0_REG32 SDIRSP1;
+ S3C24X0_REG32 SDIRSP2;
+ S3C24X0_REG32 SDIRSP3;
+ S3C24X0_REG32 SDIDTIMER;
+ S3C24X0_REG32 SDIBSIZE;
+ S3C24X0_REG32 SDIDCON;
+ S3C24X0_REG32 SDIDCNT;
+ S3C24X0_REG32 SDIDSTA;
+ S3C24X0_REG32 SDIFSTA;
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 SDIDAT;
+ S3C24X0_REG8 res[3];
+ S3C24X0_REG8 SDIDAT;
#else
- S3C24X0_REG8 SDIDAT;
- S3C24X0_REG8 res[3];
+ S3C24X0_REG8 SDIDAT;
+ S3C24X0_REG8 res[3];
#endif
- S3C24X0_REG32 SDIIMSK;
+ S3C24X0_REG32 SDIIMSK;
} /*__attribute__((__packed__))*/ S3C2410_SDI;
-
-#if 0
-/* Memory control */
-#define rBWSCON (*(volatile unsigned *)0x48000000)
-#define rBANKCON0 (*(volatile unsigned *)0x48000004)
-#define rBANKCON1 (*(volatile unsigned *)0x48000008)
-#define rBANKCON2 (*(volatile unsigned *)0x4800000C)
-#define rBANKCON3 (*(volatile unsigned *)0x48000010)
-#define rBANKCON4 (*(volatile unsigned *)0x48000014)
-#define rBANKCON5 (*(volatile unsigned *)0x48000018)
-#define rBANKCON6 (*(volatile unsigned *)0x4800001C)
-#define rBANKCON7 (*(volatile unsigned *)0x48000020)
-#define rREFRESH (*(volatile unsigned *)0x48000024)
-#define rBANKSIZE (*(volatile unsigned *)0x48000028)
-#define rMRSRB6 (*(volatile unsigned *)0x4800002C)
-#define rMRSRB7 (*(volatile unsigned *)0x48000030)
-
-
-/* USB HOST */
-#define rHcRevision (*(volatile unsigned *)0x49000000)
-#define rHcControl (*(volatile unsigned *)0x49000004)
-#define rHcCommonStatus (*(volatile unsigned *)0x49000008)
-#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C)
-#define rHcInterruptEnable (*(volatile unsigned *)0x49000010)
-#define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
-#define rHcHCCA (*(volatile unsigned *)0x49000018)
-#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C)
-#define rHcControlHeadED (*(volatile unsigned *)0x49000020)
-#define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
-#define rHcBulkHeadED (*(volatile unsigned *)0x49000028)
-#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C)
-#define rHcDoneHead (*(volatile unsigned *)0x49000030)
-#define rHcRmInterval (*(volatile unsigned *)0x49000034)
-#define rHcFmRemaining (*(volatile unsigned *)0x49000038)
-#define rHcFmNumber (*(volatile unsigned *)0x4900003C)
-#define rHcPeriodicStart (*(volatile unsigned *)0x49000040)
-#define rHcLSThreshold (*(volatile unsigned *)0x49000044)
-#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048)
-#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C)
-#define rHcRhStatus (*(volatile unsigned *)0x49000050)
-#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054)
-#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058)
-
-
-/* INTERRUPT */
-#define rSRCPND (*(volatile unsigned *)0x4A000000)
-#define rINTMOD (*(volatile unsigned *)0x4A000004)
-#define rINTMSK (*(volatile unsigned *)0x4A000008)
-#define rPRIORITY (*(volatile unsigned *)0x4A00000C)
-#define rINTPND (*(volatile unsigned *)0x4A000010)
-#define rINTOFFSET (*(volatile unsigned *)0x4A000014)
-#define rSUBSRCPND (*(volatile unsigned *)0x4A000018)
-#define rINTSUBMSK (*(volatile unsigned *)0x4A00001C)
-
-
-/* DMA */
-#define rDISRC0 (*(volatile unsigned *)0x4B000000)
-#define rDISRCC0 (*(volatile unsigned *)0x4B000004)
-#define rDIDST0 (*(volatile unsigned *)0x4B000008)
-#define rDIDSTC0 (*(volatile unsigned *)0x4B00000C)
-#define rDCON0 (*(volatile unsigned *)0x4B000010)
-#define rDSTAT0 (*(volatile unsigned *)0x4B000014)
-#define rDCSRC0 (*(volatile unsigned *)0x4B000018)
-#define rDCDST0 (*(volatile unsigned *)0x4B00001C)
-#define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020)
-#define rDISRC1 (*(volatile unsigned *)0x4B000040)
-#define rDISRCC1 (*(volatile unsigned *)0x4B000044)
-#define rDIDST1 (*(volatile unsigned *)0x4B000048)
-#define rDIDSTC1 (*(volatile unsigned *)0x4B00004C)
-#define rDCON1 (*(volatile unsigned *)0x4B000050)
-#define rDSTAT1 (*(volatile unsigned *)0x4B000054)
-#define rDCSRC1 (*(volatile unsigned *)0x4B000058)
-#define rDCDST1 (*(volatile unsigned *)0x4B00005C)
-#define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060)
-#define rDISRC2 (*(volatile unsigned *)0x4B000080)
-#define rDISRCC2 (*(volatile unsigned *)0x4B000084)
-#define rDIDST2 (*(volatile unsigned *)0x4B000088)
-#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C)
-#define rDCON2 (*(volatile unsigned *)0x4B000090)
-#define rDSTAT2 (*(volatile unsigned *)0x4B000094)
-#define rDCSRC2 (*(volatile unsigned *)0x4B000098)
-#define rDCDST2 (*(volatile unsigned *)0x4B00009C)
-#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0)
-#define rDISRC3 (*(volatile unsigned *)0x4B0000C0)
-#define rDISRCC3 (*(volatile unsigned *)0x4B0000C4)
-#define rDIDST3 (*(volatile unsigned *)0x4B0000C8)
-#define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC)
-#define rDCON3 (*(volatile unsigned *)0x4B0000D0)
-#define rDSTAT3 (*(volatile unsigned *)0x4B0000D4)
-#define rDCSRC3 (*(volatile unsigned *)0x4B0000D8)
-#define rDCDST3 (*(volatile unsigned *)0x4B0000DC)
-#define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0)
-
-
-/* CLOCK & POWER MANAGEMENT */
-#define rLOCKTIME (*(volatile unsigned *)0x4C000000)
-#define rMPLLCON (*(volatile unsigned *)0x4C000004)
-#define rUPLLCON (*(volatile unsigned *)0x4C000008)
-#define rCLKCON (*(volatile unsigned *)0x4C00000C)
-#define rCLKSLOW (*(volatile unsigned *)0x4C000010)
-#define rCLKDIVN (*(volatile unsigned *)0x4C000014)
-
-
-/* LCD CONTROLLER */
-#define rLCDCON1 (*(volatile unsigned *)0x4D000000)
-#define rLCDCON2 (*(volatile unsigned *)0x4D000004)
-#define rLCDCON3 (*(volatile unsigned *)0x4D000008)
-#define rLCDCON4 (*(volatile unsigned *)0x4D00000C)
-#define rLCDCON5 (*(volatile unsigned *)0x4D000010)
-#define rLCDSADDR1 (*(volatile unsigned *)0x4D000014)
-#define rLCDSADDR2 (*(volatile unsigned *)0x4D000018)
-#define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C)
-#define rREDLUT (*(volatile unsigned *)0x4D000020)
-#define rGREENLUT (*(volatile unsigned *)0x4D000024)
-#define rBLUELUT (*(volatile unsigned *)0x4D000028)
-#define rDITHMODE (*(volatile unsigned *)0x4D00004C)
-#define rTPAL (*(volatile unsigned *)0x4D000050)
-#define rLCDINTPND (*(volatile unsigned *)0x4D000054)
-#define rLCDSRCPND (*(volatile unsigned *)0x4D000058)
-#define rLCDINTMSK (*(volatile unsigned *)0x4D00005C)
-
-
-/* NAND FLASH */
-#define rNFCONF (*(volatile unsigned *)0x4E000000)
-#define rNFCMD (*(volatile unsigned *)0x4E000004)
-#define rNFADDR (*(volatile unsigned *)0x4E000008)
-#define rNFDATA (*(volatile unsigned *)0x4E00000C)
-#define rNFSTAT (*(volatile unsigned *)0x4E000010)
-#define rNFECC (*(volatile unsigned *)0x4E000014)
-
-
-/* UART */
-#define rULCON0 (*(volatile unsigned *)0x50000000)
-#define rUCON0 (*(volatile unsigned *)0x50000004)
-#define rUFCON0 (*(volatile unsigned *)0x50000008)
-#define rUMCON0 (*(volatile unsigned *)0x5000000C)
-#define rUTRSTAT0 (*(volatile unsigned *)0x50000010)
-#define rUERSTAT0 (*(volatile unsigned *)0x50000014)
-#define rUFSTAT0 (*(volatile unsigned *)0x50000018)
-#define rUMSTAT0 (*(volatile unsigned *)0x5000001C)
-#define rUBRDIV0 (*(volatile unsigned *)0x50000028)
-
-#define rULCON1 (*(volatile unsigned *)0x50004000)
-#define rUCON1 (*(volatile unsigned *)0x50004004)
-#define rUFCON1 (*(volatile unsigned *)0x50004008)
-#define rUMCON1 (*(volatile unsigned *)0x5000400C)
-#define rUTRSTAT1 (*(volatile unsigned *)0x50004010)
-#define rUERSTAT1 (*(volatile unsigned *)0x50004014)
-#define rUFSTAT1 (*(volatile unsigned *)0x50004018)
-#define rUMSTAT1 (*(volatile unsigned *)0x5000401C)
-#define rUBRDIV1 (*(volatile unsigned *)0x50004028)
-
-#define rULCON2 (*(volatile unsigned *)0x50008000)
-#define rUCON2 (*(volatile unsigned *)0x50008004)
-#define rUFCON2 (*(volatile unsigned *)0x50008008)
-#define rUTRSTAT2 (*(volatile unsigned *)0x50008010)
-#define rUERSTAT2 (*(volatile unsigned *)0x50008014)
-#define rUFSTAT2 (*(volatile unsigned *)0x50008018)
-#define rUBRDIV2 (*(volatile unsigned *)0x50008028)
-
-#ifdef __BIG_ENDIAN
-#define rUTXH0 (*(volatile unsigned char *)0x50000023)
-#define rURXH0 (*(volatile unsigned char *)0x50000027)
-#define rUTXH1 (*(volatile unsigned char *)0x50004023)
-#define rURXH1 (*(volatile unsigned char *)0x50004027)
-#define rUTXH2 (*(volatile unsigned char *)0x50008023)
-#define rURXH2 (*(volatile unsigned char *)0x50008027)
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x50000027)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x50004027)
-#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
-#define RdURXH2() (*(volatile unsigned char *)0x50008027)
-
-#define UTXH0 (0x50000020+3) /* byte_access address by DMA */
-#define URXH0 (0x50000024+3)
-#define UTXH1 (0x50004020+3)
-#define URXH1 (0x50004024+3)
-#define UTXH2 (0x50008020+3)
-#define URXH2 (0x50008024+3)
-
-#else /* Little Endian */
-#define rUTXH0 (*(volatile unsigned char *)0x50000020)
-#define rURXH0 (*(volatile unsigned char *)0x50000024)
-#define rUTXH1 (*(volatile unsigned char *)0x50004020)
-#define rURXH1 (*(volatile unsigned char *)0x50004024)
-#define rUTXH2 (*(volatile unsigned char *)0x50008020)
-#define rURXH2 (*(volatile unsigned char *)0x50008024)
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x50000024)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x50004024)
-#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
-#define RdURXH2() (*(volatile unsigned char *)0x50008024)
-
-#define UTXH0 (0x50000020) /* byte_access address by DMA */
-#define URXH0 (0x50000024)
-#define UTXH1 (0x50004020)
-#define URXH1 (0x50004024)
-#define UTXH2 (0x50008020)
-#define URXH2 (0x50008024)
-#endif
-
-
-/* PWM TIMER */
-#define rTCFG0 (*(volatile unsigned *)0x51000000)
-#define rTCFG1 (*(volatile unsigned *)0x51000004)
-#define rTCON (*(volatile unsigned *)0x51000008)
-#define rTCNTB0 (*(volatile unsigned *)0x5100000C)
-#define rTCMPB0 (*(volatile unsigned *)0x51000010)
-#define rTCNTO0 (*(volatile unsigned *)0x51000014)
-#define rTCNTB1 (*(volatile unsigned *)0x51000018)
-#define rTCMPB1 (*(volatile unsigned *)0x5100001C)
-#define rTCNTO1 (*(volatile unsigned *)0x51000020)
-#define rTCNTB2 (*(volatile unsigned *)0x51000024)
-#define rTCMPB2 (*(volatile unsigned *)0x51000028)
-#define rTCNTO2 (*(volatile unsigned *)0x5100002C)
-#define rTCNTB3 (*(volatile unsigned *)0x51000030)
-#define rTCMPB3 (*(volatile unsigned *)0x51000034)
-#define rTCNTO3 (*(volatile unsigned *)0x51000038)
-#define rTCNTB4 (*(volatile unsigned *)0x5100003C)
-#define rTCNTO4 (*(volatile unsigned *)0x51000040)
-
-
-/* USB DEVICE */
-#ifdef __BIG_ENDIAN
-#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143)
-#define rPWR_REG (*(volatile unsigned char *)0x52000147)
-#define rEP_INT_REG (*(volatile unsigned char *)0x5200014B)
-#define rUSB_INT_REG (*(volatile unsigned char *)0x5200015B)
-#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015F)
-#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016F)
-#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173)
-#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177)
-#define rINDEX_REG (*(volatile unsigned char *)0x5200017B)
-#define rMAXP_REG (*(volatile unsigned char *)0x52000183)
-#define rEP0_CSR (*(volatile unsigned char *)0x52000187)
-#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187)
-#define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018B)
-#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193)
-#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
-#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019B)
-#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019F)
-#define rEP0_FIFO (*(volatile unsigned char *)0x520001C3)
-#define rEP1_FIFO (*(volatile unsigned char *)0x520001C7)
-#define rEP2_FIFO (*(volatile unsigned char *)0x520001CB)
-#define rEP3_FIFO (*(volatile unsigned char *)0x520001CF)
-#define rEP4_FIFO (*(volatile unsigned char *)0x520001D3)
-#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203)
-#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207)
-#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020B)
-#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020F)
-#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000213)
-#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000217)
-#define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021B)
-#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021F)
-#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223)
-#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000227)
-#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x5200022B)
-#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022F)
-#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243)
-#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247)
-#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024B)
-#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024F)
-#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000253)
-#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000257)
-#define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025B)
-#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025F)
-#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263)
-#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000267)
-#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x5200026B)
-#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026F)
-#else /* little endian */
-#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140)
-#define rPWR_REG (*(volatile unsigned char *)0x52000144)
-#define rEP_INT_REG (*(volatile unsigned char *)0x52000148)
-#define rUSB_INT_REG (*(volatile unsigned char *)0x52000158)
-#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015C)
-#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016C)
-#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170)
-#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174)
-#define rINDEX_REG (*(volatile unsigned char *)0x52000178)
-#define rMAXP_REG (*(volatile unsigned char *)0x52000180)
-#define rEP0_CSR (*(volatile unsigned char *)0x52000184)
-#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184)
-#define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188)
-#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190)
-#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
-#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198)
-#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019C)
-#define rEP0_FIFO (*(volatile unsigned char *)0x520001C0)
-#define rEP1_FIFO (*(volatile unsigned char *)0x520001C4)
-#define rEP2_FIFO (*(volatile unsigned char *)0x520001C8)
-#define rEP3_FIFO (*(volatile unsigned char *)0x520001CC)
-#define rEP4_FIFO (*(volatile unsigned char *)0x520001D0)
-#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200)
-#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204)
-#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208)
-#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020C)
-#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000210)
-#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000214)
-#define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218)
-#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021C)
-#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220)
-#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000224)
-#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x52000228)
-#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022C)
-#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240)
-#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244)
-#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248)
-#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024C)
-#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000250)
-#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000254)
-#define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258)
-#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025C)
-#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260)
-#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000264)
-#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x52000268)
-#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026C)
-#endif /* __BIG_ENDIAN */
-
-
-/* WATCH DOG TIMER */
-#define rWTCON (*(volatile unsigned *)0x53000000)
-#define rWTDAT (*(volatile unsigned *)0x53000004)
-#define rWTCNT (*(volatile unsigned *)0x53000008)
-
-
-/* IIC */
-#define rIICCON (*(volatile unsigned *)0x54000000)
-#define rIICSTAT (*(volatile unsigned *)0x54000004)
-#define rIICADD (*(volatile unsigned *)0x54000008)
-#define rIICDS (*(volatile unsigned *)0x5400000C)
-
-
-/* IIS */
-#define rIISCON (*(volatile unsigned *)0x55000000)
-#define rIISMOD (*(volatile unsigned *)0x55000004)
-#define rIISPSR (*(volatile unsigned *)0x55000008)
-#define rIISFCON (*(volatile unsigned *)0x5500000C)
-
-#ifdef __BIG_ENDIAN
-#define IISFIF ((volatile unsigned short *)0x55000012)
-#else /* little endian */
-#define IISFIF ((volatile unsigned short *)0x55000010)
-#endif
-
-
-/* I/O PORT */
-#define rGPACON (*(volatile unsigned *)0x56000000)
-#define rGPADAT (*(volatile unsigned *)0x56000004)
-
-#define rGPBCON (*(volatile unsigned *)0x56000010)
-#define rGPBDAT (*(volatile unsigned *)0x56000014)
-#define rGPBUP (*(volatile unsigned *)0x56000018)
-
-#define rGPCCON (*(volatile unsigned *)0x56000020)
-#define rGPCDAT (*(volatile unsigned *)0x56000024)
-#define rGPCUP (*(volatile unsigned *)0x56000028)
-
-#define rGPDCON (*(volatile unsigned *)0x56000030)
-#define rGPDDAT (*(volatile unsigned *)0x56000034)
-#define rGPDUP (*(volatile unsigned *)0x56000038)
-
-#define rGPECON (*(volatile unsigned *)0x56000040)
-#define rGPEDAT (*(volatile unsigned *)0x56000044)
-#define rGPEUP (*(volatile unsigned *)0x56000048)
-
-#define rGPFCON (*(volatile unsigned *)0x56000050)
-#define rGPFDAT (*(volatile unsigned *)0x56000054)
-#define rGPFUP (*(volatile unsigned *)0x56000058)
-
-#define rGPGCON (*(volatile unsigned *)0x56000060)
-#define rGPGDAT (*(volatile unsigned *)0x56000064)
-#define rGPGUP (*(volatile unsigned *)0x56000068)
-
-#define rGPHCON (*(volatile unsigned *)0x56000070)
-#define rGPHDAT (*(volatile unsigned *)0x56000074)
-#define rGPHUP (*(volatile unsigned *)0x56000078)
-
-#define rMISCCR (*(volatile unsigned *)0x56000080)
-#define rDCLKCON (*(volatile unsigned *)0x56000084)
-#define rEXTINT0 (*(volatile unsigned *)0x56000088)
-#define rEXTINT1 (*(volatile unsigned *)0x5600008C)
-#define rEXTINT2 (*(volatile unsigned *)0x56000090)
-#define rEINTFLT0 (*(volatile unsigned *)0x56000094)
-#define rEINTFLT1 (*(volatile unsigned *)0x56000098)
-#define rEINTFLT2 (*(volatile unsigned *)0x5600009C)
-#define rEINTFLT3 (*(volatile unsigned *)0x560000A0)
-#define rEINTMASK (*(volatile unsigned *)0x560000A4)
-#define rEINTPEND (*(volatile unsigned *)0x560000A8)
-#define rGSTATUS0 (*(volatile unsigned *)0x560000AC)
-#define rGSTATUS1 (*(volatile unsigned *)0x560000B0)
-
-
-/* RTC */
-#ifdef __BIG_ENDIAN
-#define rRTCCON (*(volatile unsigned char *)0x57000043)
-#define rTICNT (*(volatile unsigned char *)0x57000047)
-#define rRTCALM (*(volatile unsigned char *)0x57000053)
-#define rALMSEC (*(volatile unsigned char *)0x57000057)
-#define rALMMIN (*(volatile unsigned char *)0x5700005B)
-#define rALMHOUR (*(volatile unsigned char *)0x5700005F)
-#define rALMDATE (*(volatile unsigned char *)0x57000063)
-#define rALMMON (*(volatile unsigned char *)0x57000067)
-#define rALMYEAR (*(volatile unsigned char *)0x5700006B)
-#define rRTCRST (*(volatile unsigned char *)0x5700006F)
-#define rBCDSEC (*(volatile unsigned char *)0x57000073)
-#define rBCDMIN (*(volatile unsigned char *)0x57000077)
-#define rBCDHOUR (*(volatile unsigned char *)0x5700007B)
-#define rBCDDATE (*(volatile unsigned char *)0x5700007F)
-#define rBCDDAY (*(volatile unsigned char *)0x57000083)
-#define rBCDMON (*(volatile unsigned char *)0x57000087)
-#define rBCDYEAR (*(volatile unsigned char *)0x5700008B)
-#else /* little endian */
-#define rRTCCON (*(volatile unsigned char *)0x57000040)
-#define rTICNT (*(volatile unsigned char *)0x57000044)
-#define rRTCALM (*(volatile unsigned char *)0x57000050)
-#define rALMSEC (*(volatile unsigned char *)0x57000054)
-#define rALMMIN (*(volatile unsigned char *)0x57000058)
-#define rALMHOUR (*(volatile unsigned char *)0x5700005C)
-#define rALMDATE (*(volatile unsigned char *)0x57000060)
-#define rALMMON (*(volatile unsigned char *)0x57000064)
-#define rALMYEAR (*(volatile unsigned char *)0x57000068)
-#define rRTCRST (*(volatile unsigned char *)0x5700006C)
-#define rBCDSEC (*(volatile unsigned char *)0x57000070)
-#define rBCDMIN (*(volatile unsigned char *)0x57000074)
-#define rBCDHOUR (*(volatile unsigned char *)0x57000078)
-#define rBCDDATE (*(volatile unsigned char *)0x5700007C)
-#define rBCDDAY (*(volatile unsigned char *)0x57000080)
-#define rBCDMON (*(volatile unsigned char *)0x57000084)
-#define rBCDYEAR (*(volatile unsigned char *)0x57000088)
-#endif
-
-
-/* ADC */
-#define rADCCON (*(volatile unsigned *)0x58000000)
-#define rADCTSC (*(volatile unsigned *)0x58000004)
-#define rADCDLY (*(volatile unsigned *)0x58000008)
-#define rADCDAT0 (*(volatile unsigned *)0x5800000C)
-#define rADCDAT1 (*(volatile unsigned *)0x58000010)
-
-
-/* SPI */
-#define rSPCON0 (*(volatile unsigned *)0x59000000)
-#define rSPSTA0 (*(volatile unsigned *)0x59000004)
-#define rSPPIN0 (*(volatile unsigned *)0x59000008)
-#define rSPPRE0 (*(volatile unsigned *)0x5900000C)
-#define rSPTDAT0 (*(volatile unsigned *)0x59000010)
-#define rSPRDAT0 (*(volatile unsigned *)0x59000014)
-#define rSPCON1 (*(volatile unsigned *)0x59000020)
-#define rSPSTA1 (*(volatile unsigned *)0x59000024)
-#define rSPPIN1 (*(volatile unsigned *)0x59000028)
-#define rSPPRE1 (*(volatile unsigned *)0x5900002C)
-#define rSPTDAT1 (*(volatile unsigned *)0x59000030)
-#define rSPRDAT1 (*(volatile unsigned *)0x59000034)
-
-
-/* SD INTERFACE */
-#define rSDICON (*(volatile unsigned *)0x5A000000)
-#define rSDIPRE (*(volatile unsigned *)0x5A000004)
-#define rSDICmdArg (*(volatile unsigned *)0x5A000008)
-#define rSDICmdCon (*(volatile unsigned *)0x5A00000C)
-#define rSDICmdSta (*(volatile unsigned *)0x5A000010)
-#define rSDIRSP0 (*(volatile unsigned *)0x5A000014)
-#define rSDIRSP1 (*(volatile unsigned *)0x5A000018)
-#define rSDIRSP2 (*(volatile unsigned *)0x5A00001C)
-#define rSDIRSP3 (*(volatile unsigned *)0x5A000020)
-#define rSDIDTimer (*(volatile unsigned *)0x5A000024)
-#define rSDIBSize (*(volatile unsigned *)0x5A000028)
-#define rSDIDatCon (*(volatile unsigned *)0x5A00002C)
-#define rSDIDatCnt (*(volatile unsigned *)0x5A000030)
-#define rSDIDatSta (*(volatile unsigned *)0x5A000034)
-#define rSDIFSTA (*(volatile unsigned *)0x5A000038)
-#ifdef __BIG_ENDIAN
-#define rSDIDAT (*(volatile unsigned char *)0x5A00003F)
-#else
-#define rSDIDAT (*(volatile unsigned char *)0x5A00003C)
-#endif
-#define rSDIIntMsk (*(volatile unsigned *)0x5A000040)
-
-#endif
-
#endif /*__S3C24X0_H__*/
-- 1.6.0.6
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