[U-Boot] TSEC ethernet controller problems (crc errors/ corruption)

[dwh at ovro.caltech.edu]

Hi Kim,

The bit setting did not help with our errors at
1Gbit, so the comment:

> While not making a difference on the MPC8349EMDS,
> changing the output buffer impedance on TSEC1 to
> 2.5V has negative effect on other mpc83xx based
> boards - they start dropping frame data
> consequently prompting TSEC errors and a
> general loss of 1000mbit networking.

May not actually be relevant, this was more of
a cleanup to make the source consistent with the
user manual.

Perhaps something like the following comment:

  In GMII mode (which operates at 3.3V) both SICRH
  TSEC1/2 output buffer impedance bits should be
  clear, i.e., SICRH[TSIOB1] = 0 and SICRH[TSIOB2] = 0.
  SICRH[TSIOB1] was erroneously being set high.

As far as debugging our error goes, we're going to
try a different clock source on the PHY. Currently
its 125MHz, but the PHY can use 25MHz. We'll put
a synthesizer on the pin, adjust the operating
frequency around nominal, and see if we can make
our problem with 1Gbit mode worse, so we can figure
our what our real problem is.

Cheers,
Dave