[U-Boot] 88e61xx driver in u-boot

[Prafulla Wadaskar]

> -----Original Message-----
> From: Andrew Dyer [mailto:amdyer at gmail.com] 
> Sent: Wednesday, June 24, 2009 4:55 AM
> To: Prafulla Wadaskar; U-Boot List
> Subject: 88e61xx driver in u-boot
> 
> Hi, I am in the midst of bringing up a board using the 
> 88E6161 chip and was looking at your u-boot driver as an 
> example of how to set it up (still writing simple tests 
> loaded via JTAG, not the full u-boot).
> 
> Our board uses the indirect method of writing to the MII bus 
> registers, and I think there may be a bug in the indirect 
> version of mv88e61xx_rd_phy().  In the function, the command 
> written into the SMI indirect command register is:
> 
>   86        miiphy_write(name, mii_dev_addr, 0x0,
>   87                      reg_ofs | (phy_adr << 5) | (1 << 10) | (1 <<
> 12) | (1 <<
>   88
>        15));
> 
> The part that looks wrong is the 1 << 10  (the SMIOp field).
> According to the datasheet table 35, for a read to be 
> performed inside the chip it should be 2 << 10.  Probably cut 
> and pasted from the
> mv88e61xx_wr_phy() above.
I have tested single chip addressing mode, Multichip addressing mode is not tested for this driver, I am getting the board this weekend, I will check and reply
But looking at your analysis, it seems to be copy paste error, I will correct it.
Thanks....
 
> 
> 
> I also wondered about this snippet of code:
> 
>   55 static void mv88e61xx_wr_phy(char *name, u32 phy_adr, 
> u32 reg_ofs, u16 data)
>   56 {
>   57         u16 reg;
>   58         u32 mii_dev_addr;
>   59
>   60         /* command to read PHY dev address */
>   61         if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
>   62                 printf("Error..could not read PHY dev
> address\n");
>   63                return;
>   64         }
> 
> I don't see anything in the 88E6161 switch itself that would 
> respond at those 0xEE addresses (IIRC the MII bus only 
> provides for 5 bits of register and phy address).  Is this 
> something specific to the board/SoC you were running the 
> switch with and/or it's miiphy_read implementation?
> 
> As far as I can tell, what is needed is to set mii_dev_addr 
> to the address set by the ADDR[4:0] chip config pins, which 
> would see to be a board specific item, and shouldn't be in 
> the generic driver.  This would seem like a good candidate 
> for something that is passed in via the mv88e61xx_config structure.

This command is mapped to the smi_reg_read function of SoCs eth controller driver (kirkwood-egiga.c).
The 0xEE in this command is used to flag the above function to read-n-return phy device address which is needed by switch for multi chip addressing.
Phy device address is decided by board hardware and same need to be programmed for eth controller and switch for successful read/write.
In the current implementation phy address is provided to eth controller driver from board config header.
During switch init which comes next, switch gets it from associated controller though this interface

As you suggested, we can simply provide this through mv88e61xx_config structure, but it may lead to configuration problems, providing same settings at two different places, if there is mismatch one need to spend enough time debugging the same (as I spend).

To avoid this I have implemented above method.
We do not have exposed api for the same in miiphy.h, this need to be supported in miiphyutil
My next efforts will be expose miiphy_devadr_read/write api for the same.

Regards..
Prafulla ..
 
>