[U-Boot] Uboot and ARM SMP support

[Shilimkar, Santosh]

> -----Original Message-----
> From: Pandita, Vikram 
> Sent: Thursday, June 25, 2009 6:32 PM
> To: Jean-Christophe PLAGNIOL-VILLARD; Nishanth Menon; 
> Shilimkar, Santosh
> Cc: Sudeep K N; u-boot at lists.denx.de; Tom
> Subject: RE: [U-Boot] Uboot and ARM SMP support
> 
> Adding Santosh to loop who has pushed the OMAP4 SMP support 
> into Kernel.org
> 
> 
> >-----Original Message-----
> >From: Jean-Christophe PLAGNIOL-VILLARD [mailto:plagnioj at jcrosoft.com]
> >Sent: Thursday, June 25, 2009 7:44 AM
> >To: Nishanth Menon
> >Cc: Sudeep K N; u-boot at lists.denx.de; Pandita, Vikram; Tom
> >Subject: Re: [U-Boot] Uboot and ARM SMP support
> >
> >On 12:47 Thu 25 Jun     , Nishanth Menon wrote:
> >> Sudeep K N said the following on 06/25/2009 12:11 PM:
> >> > Sorry, may be I confused you.
> >> > I indent to use only one core for u-boot.
> >> > I wanted to ask whether we need to update the cache
> >> > management to boot for ARM Cortex A9 SMP if we take
> >> > ARM Cortex A8 code as base.
> >> > I have tried and did not require any change on top of A8 code
> >> > to run u-boot on A9 SMP.
> >> > Is that right approach?
> >> >
> >> >
> >> you may want to see [1] how this was done for OMAP4 (which 
> has a SMP
> >> cortex A9)-> we can discuss how to setup cortex_a9 in 
> mainline u-boot.
> >>
> >> My thought would be: cpu/arm_cortexa9 - considering that 
> a9 cores could
> >> be from 1 to 4 or so if my memory serves right -> btw, I 
> wonder how SMP
> >> handling is done in u-boot today..
> >for arm I've only a theorical design as I've no SMP board for now
> >but I want to see SMP boot & AMP boot supported in Mainline
> >

The approach is perfect and that's what is most of the SMP systems are doing..
If one look at the linux framework, U-boot need not know about the secondary cores.

As far as caches goes, the SCU is not enabled at u-boot level so there is no coherency
between L1 caches.L2 is external and not enabled at u-boot level for time being.
At the point when u-boot transfer control to kernel, the caches are flushed in the 
clean-up path so you need not do any explicit stuff.

In case you want to enable L2 cache ( if preset ), then you need to add support for 
that in the u-boot. 

So essentially u-boot would be almost same as Cortex-A8 except you should avoid programming AuxControl
register because the bit definitions are different.

Hope this helps

Regards,
Santosh