[U-Boot] [PATCH 2/6 v2] 8xx, icache: enabling ICache not before running from RAM

[Heiko Schocher]

with the new CONFIG_SYS_DELAYED_ICACHE config option, ICache
is not enabled before code runs from RAM.

Signed-off-by: Heiko Schocher <hs at denx.de>
---
 README                    |    5 +++++
 cpu/mpc8xx/start.S        |    2 +-
 include/configs/FLAGADM.h |    3 +++
 include/configs/IP860.h   |    3 +++
 include/configs/pcu_e.h   |    3 +++
 lib_ppc/board.c           |    3 +--
 6 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/README b/README
index 43fb1c0..46181a4 100644
--- a/README
+++ b/README
@@ -318,6 +318,11 @@ The following options need to be configured:
 		that this requires a (stable) reference clock (32 kHz
 		RTC clock or CONFIG_SYS_8XX_XIN)

+		CONFIG_SYS_DELAYED_ICACHE
+
+		Define this option if you want to enable the
+		ICache only when Code runs from RAM.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO

diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S
index 45c902e..8864c37 100644
--- a/cpu/mpc8xx/start.S
+++ b/cpu/mpc8xx/start.S
@@ -142,7 +142,7 @@ boot_warm:
 	lis	r3, IDC_DISABLE at h	/* Disable data cache */
 	mtspr	DC_CST, r3

-#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM))
+#if !defined(CONFIG_SYS_DELAYED_ICACHE)
 					/* On IP860 and PCU E,
 					 * we cannot enable IC yet
 					 */
diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h
index d831238..0f4277c 100644
--- a/include/configs/FLAGADM.h
+++ b/include/configs/FLAGADM.h
@@ -173,6 +173,9 @@
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */

 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
index b9c5713..125aa6c 100644
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -209,6 +209,9 @@
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */

 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
index 9214519..7c2bf1b 100644
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@@ -246,6 +246,9 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */

 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 6d29303..f69c5f4 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -736,8 +736,7 @@ void board_init_r (gd_t *id, ulong dest_addr)

 	WATCHDOG_RESET();

-#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \
-	defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
+#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83XX)
 	icache_enable ();	/* it's time to enable the instruction cache */
 #endif

-- 
1.6.0.6

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany