[U-Boot] MMU/PPC question

[Grant Likely]

On Tue, Mar 17, 2009 at 2:44 PM, SortaSBS Guy <sortasbsguy at yahoo.com> wrote:
>
>    I'm working on a u-boot port to custom hardware based on the Lite5200B board, with a MPC5200 processor. u-boot is working great (can boot from 16-bit flash, SDRAM is working and I can boot linux!) but now I'm working through some MMU configuration issues, and had a few general questions:
>
> 1. Does u-boot/linux make any assumptions about how particular BAT registers are used? For example, we're not using PCI, and I was going to use those BAT registers to cover some memory-mapped peripheral I/O space (ex: icecube.c, DBAT3 and 4 are used for PCI, so I would use them instead for our I/O ranges.)

Linux doesn't care what U-Boot did and reloads the BATs during kernel
initialization.  A few of the BATs are used for RAM, other than that
they are free.  However, you cannot just chose any part of the virtual
address space when turning on BATs for IO because the kernel has its
own scheme for slicing up the virtual address space.  Space needs to
be allocated in the virtual address space before a BAT can be mapped
to it.

I actually have a series of patches which make allocation and setting
up BATs for IO really easy, but I need to massage it some more before
I can resubmit.  I'll try to remember to cc: you when I post them.  If
you don't see them in a couple of weeks, then email me again to ask.

> 2. Do you need a separate BAT register for each memory mapped I/O space? We have 4 chip selects, but could I arrange the chip selects to use a contiguous range and presumably cover that with a single BAT register?

No.  If they all fit within the BAT range then they can be mapped with
the same bat (assuming all of them want the same
cacheable/cache-inhibited setting).

> 3. Would I need separate BAT registers for 8-bit vs. 16-bit devices?

No.  BAT settings are completely independent of CS configuration.

>
>    Also, maybe slightly off topic, but has anyone had problems using 8-bit peripherals on the MPC52000 in large flash mode? I'm seeing some odd behavior that looks as though the internal PPC bus thinks 8-bit data is on bits 8-15 and only ever reads/writes zeros, and the external data lines (d0-d7) show correct data for reads, and only shows correct data for odd-address writes.

I don't know, sorry.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.