[U-Boot] [PATCH] board support patch for phyCORE-MPC5200B-tiny

Jon Smirl jonsmirl at gmail.com
Sat Mar 21 19:20:20 CET 2009


Add support for the Phytec phyCORE-MPC5200B-tiny. This code is from Pengutronix.de but they
didn't sign the patch. I have updated it from u-boot 1.2 to work on u-boot master.

Signed-off-by: Jon Smirl <jonsmirl at gmail.com>

Signed-off-by: Jon Smirl <jonsmirl at gmail.com>

---
 Makefile                                           |   16 +
 board/phycore_mpc5200b_tiny/Makefile               |   50 ++
 board/phycore_mpc5200b_tiny/config.mk              |   43 ++
 board/phycore_mpc5200b_tiny/mt46v32m16-75.h        |   54 +++
 .../phycore_mpc5200b_tiny/phycore_mpc5200b_tiny.c  |  307 ++++++++++++++
 board/phycore_mpc5200b_tiny/u-boot.lds             |  123 ++++++
 cpu/mpc5xxx/ide.c                                  |    3 
 include/configs/phycore_mpc5200b_tiny.h            |  431 ++++++++++++++++++++
 8 files changed, 1027 insertions(+), 0 deletions(-)
 create mode 100644 board/phycore_mpc5200b_tiny/Makefile
 create mode 100644 board/phycore_mpc5200b_tiny/config.mk
 create mode 100644 board/phycore_mpc5200b_tiny/mt46v32m16-75.h
 create mode 100644 board/phycore_mpc5200b_tiny/phycore_mpc5200b_tiny.c
 create mode 100644 board/phycore_mpc5200b_tiny/u-boot.lds
 create mode 100644 include/configs/phycore_mpc5200b_tiny.h

diff --git a/Makefile b/Makefile
index ba6a602..fe6dd5b 100644
--- a/Makefile
+++ b/Makefile
@@ -668,6 +668,22 @@ o2dnt_config:	unconfig
 pf5200_config:	unconfig
 	@$(MKCONFIG) pf5200  ppc mpc5xxx pf5200 esd
 
+phycore_mpc5200b_tiny_config \
+phycore_mpc5200b_tiny_LOWBOOT_config \
+phycore_mpc5200b_tiny_RAMBOOT_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFF000000"	>board/phycore_mpc5200b_tiny/config.tmp ; \
+		  echo "... with LOWBOOT configuration" ; \
+		}
+	@[ -z "$(findstring RAMBOOT_,$@)" ] || \
+		{ echo "TEXT_BASE = 0x00100000"	>board/phycore_mpc5200b_tiny/config.tmp ; \
+		  echo "... with RAMBOOT configuration" ; \
+		  echo "... remember to make sure that MBAR is already switched to 0xF0000000 !!!" ; \
+		}
+	@$(MKCONFIG) -a phycore_mpc5200b_tiny ppc mpc5xxx phycore_mpc5200b_tiny
+	@ echo "remember to set PHYCORE_MPC5200B_TINY_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1"
+
 PM520_config \
 PM520_DDR_config \
 PM520_ROMBOOT_config \
diff --git a/board/phycore_mpc5200b_tiny/Makefile b/board/phycore_mpc5200b_tiny/Makefile
new file mode 100644
index 0000000..22ce8e6
--- /dev/null
+++ b/board/phycore_mpc5200b_tiny/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/phycore_mpc5200b_tiny/config.mk b/board/phycore_mpc5200b_tiny/config.mk
new file mode 100644
index 0000000..e16959f
--- /dev/null
+++ b/board/phycore_mpc5200b_tiny/config.mk
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# phyCORE-MPC5200B tiny board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFF000000   boot low
+#	0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+## TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/phycore_mpc5200b_tiny/mt46v32m16-75.h b/board/phycore_mpc5200b_tiny/mt46v32m16-75.h
new file mode 100644
index 0000000..4b501c6
--- /dev/null
+++ b/board/phycore_mpc5200b_tiny/mt46v32m16-75.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
+ *
+ * Eric Schumann, Phytec Messtechnik
+ * adapted for mt46v32m16-75 DDR-RAM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x71500F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x47770000
+
+/*
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x715f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+*/
+
+/* Settings for XLB = 99 MHz */
+/*
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714b0f00
+#define SDRAM_CONFIG1	0x63611730
+#define SDRAM_CONFIG2	0x47670000
+*/
+
+#define SDRAM_TAPDELAY	0x10000000 /* reserved Bit in MPC5200 B3-Step */
diff --git a/board/phycore_mpc5200b_tiny/phycore_mpc5200b_tiny.c b/board/phycore_mpc5200b_tiny/phycore_mpc5200b_tiny.c
new file mode 100644
index 0000000..4e7674e
--- /dev/null
+++ b/board/phycore_mpc5200b_tiny/phycore_mpc5200b_tiny.c
@@ -0,0 +1,307 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messtechnik GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#ifdef CONFIG_VIDEO_OPENIP
+#include <openip.h>
+#endif
+
+#include "mt46v32m16-75.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set CDM clock enable register, set MPC5200B SDRAM bus to reduced driver strength */
+	*(vu_long *)MPC5XXX_CDM_CLK_ENA = 0x00CFFFFF;
+	__asm__ volatile ("sync");
+
+
+
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR && SDRAM_TAPDELAY
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: phyCORE-MPC5200B-tiny\n");
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+#define GPIO_PSC2_4	0x02000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+    	/* Configure PSC2_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC2_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC2_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC2_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC2_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC2_4;
+	}
+}
+#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
+
+#ifdef CONFIG_VIDEO_OPENIP
+
+#define DISPLAY_WIDTH   320
+#define DISPLAY_HEIGHT  240
+
+#ifdef CONFIG_VIDEO_OPENIP_8BPP
+#error CONFIG_VIDEO_OPENIP_8BPP not supported.
+#endif /* CONFIG_VIDEO_OPENIP_8BPP */
+
+#ifdef CONFIG_VIDEO_OPENIP_16BPP
+#error CONFIG_VIDEO_OPENIP_16BPP not supported.
+#endif /* CONFIG_VIDEO_OPENIP_16BPP */
+#ifdef CONFIG_VIDEO_OPENIP_32BPP
+
+
+
+static const SMI_REGS init_regs [] =
+{
+	{0x00008, 0x0248013f},
+	{0x0000c, 0x021100f0},
+	{0x00010, 0x018c0106},
+	{0x00014, 0x00800000},
+	{0x00018, 0x00800000},
+	{0x00000, 0x00003701},
+	{0, 0}
+};
+#endif /* CONFIG_VIDEO_OPENIP_32BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1) {
+		strcpy (info, " Board: phyCORE-MPC5200B tiny (Phytec Messtechnik GmbH)");
+	} else if (line_number == 2) {
+		strcpy (info, "    on a PCM-980 baseboard");
+	}
+	else {
+		info [0] = '\0';
+	}
+}
+#endif
+
+/*
+ * Returns OPENIP register base address. First thing called in the driver.
+ */
+unsigned int board_video_init (void)
+{
+ulong dummy;
+dummy  = *(vu_long *)OPENIP_MMIO_BASE; /*dummy read*/
+dummy  = *(vu_long *)OPENIP_MMIO_BASE; /*dummy read*/
+	return OPENIP_MMIO_BASE;
+}
+
+/*
+ * Returns OPENIP framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+
+	return OPENIP_FB_BASE;
+}
+
+/*
+ * Called after initializing the OPENIP and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+	return init_regs;
+}
+
+int board_get_width (void)
+{
+	return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+	return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_OPENIP */
diff --git a/board/phycore_mpc5200b_tiny/u-boot.lds b/board/phycore_mpc5200b_tiny/u-boot.lds
new file mode 100644
index 0000000..7bd6d4d
--- /dev/null
+++ b/board/phycore_mpc5200b_tiny/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c
index 9e8f29b..0129180 100644
--- a/cpu/mpc5xxx/ide.c
+++ b/cpu/mpc5xxx/ide.c
@@ -45,6 +45,9 @@ int ide_preinit (void)
 #if defined(CONFIG_SYS_ATA_CS_ON_I2C2)
 	/* ATA cs0/1 on i2c2 clk/io */
 	reg = (reg & ~0x03000000ul) | 0x02000000ul;
+#elif defined(CONFIG_PHYCORE_MPC5200B_TINY)
+	/* ATA cs0/1 on Timer 0/1 */
+	reg = (reg & ~0x03000000ul) | 0x03000000ul;
 #else
 	/* ATA cs0/1 on Local Plus cs4/5 */
 	reg = (reg & ~0x03000000ul) | 0x01000000ul;
diff --git a/include/configs/phycore_mpc5200b_tiny.h b/include/configs/phycore_mpc5200b_tiny.h
new file mode 100644
index 0000000..89e660b
--- /dev/null
+++ b/include/configs/phycore_mpc5200b_tiny.h
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messatechnik GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* #define DEBUG */
+
+#define CONFIG_BOARDINFO	 "Phytec Phycore mpc5200b tiny"
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+High Level Configuration Options
+(easy to change)
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_MPC5xxx		1		/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1		/* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200_DDR	1		/* (with DDR-SDRAM) */
+#define CONFIG_PHYCORE_MPC5200B_TINY 1		/* ... on phyCORE-MPC5200B -> FEC configuration and IDE */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 	/* ... running at 33.333333MHz */
+#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02		/* Software reboot	     */
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+Serial console configuration
+-----------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_PSC_CONSOLE	3		/* console is on PSC3 -> define gps port conf. register later on to enable UART function! */
+#define CONFIG_BAUDRATE		115200		/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+
+#define	CONFIG_TIMESTAMP	1		/* Print image info with timestamp */
+
+#if (TEXT_BASE == 0xFF000000)			/* Boot low */
+	#define CONFIG_SYS_LOWBOOT 1
+#endif
+/* RAMBOOT will be defined automatically in memory section */
+
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT 		"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT   	"mtdparts=physmap-flash.0:256k(ubootl),1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+Autobooting
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_BOOTDELAY	3   /* autoboot after 3 seconds */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process even with bootdelay=0 */
+#undef	CONFIG_BOOTARGS
+
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run bootcmd_net\" to load Kernel over TFTP and to mount root filesystem over NFS;" \
+	"echo"
+
+#if 0
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"mtdparts=mtdparts=physmap-flash.0:256k(ubootl),1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)\0" \
+	"ipaddr=192.168.23.226\0"					\
+	"netmask=255.255.255.0\0"					\
+	"serverip=192.168.23.1\0"					\
+	"gateway=192.168.23.1\0"					\
+	"uimage=uImage-pcm030\0"				\
+	"oftree=oftree-pcm030.dtb\0"				\
+	"jffs2=root-pcm030.jffs2\0" 				\
+	"uboot=u-boot-pcm030.bin\0"					\
+	"bargs_base=setenv bootargs console=ttyPSC0,$(baudrate) $(mtdparts) rw\0" \
+	"bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2 rootfstype=jffs2\0" \
+	"bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+	"bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage); tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
+	"bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - 0xfff40000\0" \
+	"prg_kernel=tftp 0x400000 $(uimage); erase 0xff040000 0xff1fffff; cp.b 0x400000 0xff040000 $(filesize)\0" \
+	"prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; cp.b 0x400000 0xff200000 $(filesize)\0" \
+	"prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff; cp.b 0x400000 0xfff40000 $(filesize)\0" \
+	"update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff; cp.b 0x400000 0xFFF00000 $(filesize)\0" \
+	"unlock=yes\0" \
+	""
+#endif
+
+#define CONFIG_BOOTCOMMAND		"run bcmd_flash"
+
+/*--------------------------------------------------------------------------
+IPB Bus clocking configuration.
+ ---------------------------------------------------------------------------*/
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*-------------------------------------------------------------------------
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ *  -----------------------------------------------------------------------*/
+#define CONFIG_PCI			1
+#define CONFIG_PCI_PNP			1
+#define CONFIG_PCI_SCAN_SHOW		1
+#define CONFIG_PCI_MEM_BUS		0x40000000
+#define CONFIG_PCI_MEM_PHYS		CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE		0x10000000
+#define CONFIG_PCI_IO_BUS		0x50000000
+#define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE		0x01000000
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+ I2C configuration
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C			1		/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2		/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_SPEED		100000 		/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+ EEPROM CAT24WC32 configuration
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52		/* 1010100x */
+#define CONFIG_SYS_I2C_FACT_ADDR	0x52		/* EEPROM CAT24WC32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2		/* Bytes of address */
+#define CONFIG_SYS_EEPROM_SIZE		2048
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+RTC configuration
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define RTC
+#define CONFIG_RTC_PCF8563		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+ Flash configuration
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_FLASH_CFI		1		/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1			/* Use the common driver */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_SECT	260		/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	 	/* max num of flash banks (= chip selects) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Use also hardware protection. This seems required, as the BDI uses hardware protection
+ * Without this, U-Boot can't work with this sectors, as its protection is software only by default
+ */
+#define CONFIG_SYS_FLASH_PROTECTION	1
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+ Environment settings
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#if 0
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xfe0000)
+	#define CONFIG_ENV_SIZE		0x20000
+	#define CONFIG_ENV_SECT_SIZE	0x20000
+#else
+	#define CONFIG_ENV_IS_IN_EEPROM	1
+	#define CONFIG_ENV_OFFSET	0x00			/* environment starts at the beginning of the EEPROM */
+	#define CONFIG_ENV_SIZE		2048
+#endif
+#define CONFIG_ENV_OVERWRITE	1
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+  Memory map
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_SYS_MBAR			0xF0000000 		/* MBAR hast to be switched by other bootloader or debugger config  */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128			/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)		/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)		/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)		/* Initial Memory map for Linux */
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+ Ethernet configuration
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_MPC5xxx_FEC		1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR			0x01
+
+/*---------------------------------------------------------------------------
+ GPIO configuration
+ ---------------------------------------------------------------------------*/
+
+/* GPIO port configuration
+ *
+ * Pin mapping:
+ *
+ * [29:31] = 01x
+ * PSC1_0 -> AC97 SDATA out
+ * PSC1_1 -> AC97 SDTA in
+ * PSC1_2 -> AC97 SYNC out
+ * PSC1_3 -> AC97 bitclock out
+ * PSC1_4 -> AC97 reset out
+ *
+ * [25:27] = 001
+ * PSC2_0 -> CAN 1 Tx out
+ * PSC2_1 -> CAN 1 Rx in
+ * PSC2_2 -> CAN 2 Tx out
+ * PSC2_3 -> CAN 2 Rx in
+ * PSC2_4 -> GPIO (claimed for ATA reset, active low)
+ *
+ *
+ * [20:23] = 1100
+ * PSC3_0 -> UART Tx out
+ * PSC3_1 -> UART Rx in
+ * PSC3_2 -> UART RTS (in/out FIXME)
+ * PSC3_3 -> UART CTS (in/out FIXME)
+ * PSC3_4 -> LocalPlus Bus CS6 \
+ * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
+ * PSC3_6 -> dedicated SPI MOSI out (master case)
+ * PSC3_7 -> dedicated SPI MISO in (master case)
+ * PSC3_8 -> dedicated SPI SS out (master case)
+ * PSC3_9 -> dedicated SPI CLK out (master case)
+ *
+ * [18:19] = 01
+ * USB_0 -> USB OE out
+ * USB_1 -> USB Tx- out
+ * USB_2 -> USB Tx+ out
+ * USB_3 -> USB RxD (in/out FIXME)
+ * USB_4 -> USB Rx+ in
+ * USB_5 -> USB Rx- in
+ * USB_6 -> USB PortPower out
+ * USB_7 -> USB speed out
+ * USB_8 -> USB suspend (in/out FIXME)
+ * USB_9 -> USB overcurrent in
+ *
+ * [17] = 0
+ * USB differential mode
+ *
+ * [16] = 0
+ * PCI enabled
+ *
+ * [12:15] = 0101
+ * ETH_0 -> ETH Txen
+ * ETH_1 -> ETH TxD0
+ * ETH_2 -> ETH TxD1
+ * ETH_3 -> ETH TxD2
+ * ETH_4 -> ETH TxD3
+ * ETH_5 -> ETH Txerr
+ * ETH_6 -> ETH MDC
+ * ETH_7 -> ETH MDIO
+ * ETH_8 -> ETH RxDv
+ * ETH_9 -> ETH RxCLK
+ * ETH_10 -> ETH Collision
+ * ETH_11 -> ETH TxD
+ * ETH_12 -> ETH RxD0
+ * ETH_13 -> ETH RxD1
+ * ETH_14 -> ETH RxD2
+ * ETH_15 -> ETH RxD3
+ * ETH_16 -> ETH Rxerr
+ * ETH_17 -> ETH CRS
+ *
+ * [9:11] = 101
+ * PSC6_0 -> UART RxD in
+ * PSC6_1 -> UART CTS (in/out FIXME)
+ * PSC6_2 -> UART TxD out
+ * PSC6_3 -> UART RTS (in/out FIXME)
+ *
+ * [2:3/6:7] = 00/11
+ * TMR_0 -> ATA_CS0 out
+ * TMR_1 -> ATA_CS1 out
+ * TMR_2 -> GPIO
+ * TMR_3 -> GPIO
+ * TMR_4 -> GPIO
+ * TMR_5 -> GPIO
+ * TMR_6 -> GPIO
+ * TMR_7 -> GPIO
+ * I2C_0 -> I2C 1 Clock out
+ * I2C_1 -> I2C 1 IO in/out
+ * I2C_2 -> I2C 2 Clock out
+ * I2C_3 -> I2C 2 IO in/out
+ *
+ * [4] = 1
+ * PSC3_5 is used as CS7
+ *
+ * [5] = 1
+ * PSC3_4 is used as CS6
+ *
+ * [1] = 0
+ * gpio_wkup_7 is GPIO
+ *
+ * [0] = 0
+ * gpio_wkup_6 is GPIO
+ *
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x0f551c12
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+ Miscellaneous configurable options
+------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"uboot> "	/* Monitor Command Prompt   */
+
+#define CONFIG_CMDLINE_EDITING		1		/* add command line history	*/
+
+#define CONFIG_SYS_CACHELINE_SIZE	32		/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CACHELINE_SHIFT 5	/* log base 2 of the above value */
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#else
+	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE 		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START 	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END	 	0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+ Various low-level settings
+-----------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+/* no burst access on the LPB */
+#define CONFIG_SYS_CS_BURST		0x00000000
+/* one deadcycle for the 33MHz statemachine */
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333331
+/* one additional waitstate for the 33MHz statemachine */
+#define CONFIG_SYS_BOOTCS_CFG		0x0001dd00
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_RESET_ADDRESS 	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK		0x0001BBBB
+#define CONFIG_USB_CONFIG		0x00001000
+
+/*---------------------------------------------------------------------------
+ IDE/ATA stuff Supports IDE harddisk
+----------------------------------------------------------------------------*/
+
+#undef  CONFIG_IDE_8xx_PCCARD				/* Use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_DIRECT				/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED					/* LED   for ide not supported	*/
+#define	CONFIG_IDE_RESET		1		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2		/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE		4
+#define CONFIG_ATAPI			1
+
+/* we enable IDE and FAT support, so we also need partition support */
+#define CONFIG_DOS_PARTITION    1
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+
+#define OF_CPU				"PowerPC,5200 at 0"
+#define OF_TBCLK			CONFIG_SYS_MPC5XXX_CLKIN
+#define OF_SOC                  	"soc5200 at f0000000"
+#define OF_STDOUT_PATH			"/soc5200 at f0000000/serial at 2400"
+
+#define CONFIG_API
+
+#endif /* __CONFIG_H */



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