[U-Boot] [PATCH 02/32] Blackfin: fix SWRST/SYSCR register sizes

[Mike Frysinger]

Signed-off-by: Mike Frysinger <vapier at gentoo.org>
---
 include/asm-blackfin/mach-bf561/BF561_cdef.h       |   12 ++++++------
 .../mach-common/ADSP-EDN-extended_cdef.h           |    6 +++---
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/include/asm-blackfin/mach-bf561/BF561_cdef.h
index d8883f3..e2c165a 100644
--- a/include/asm-blackfin/mach-bf561/BF561_cdef.h
+++ b/include/asm-blackfin/mach-bf561/BF561_cdef.h
@@ -244,9 +244,9 @@
 #define pSICA_SWRST                    ((uint16_t volatile *)SICA_SWRST)
 #define bfin_read_SICA_SWRST()         bfin_read16(SICA_SWRST)
 #define bfin_write_SICA_SWRST(val)     bfin_write16(SICA_SWRST, val)
-#define pSICA_SYSCR                    ((uint32_t volatile *)SICA_SYSCR)
-#define bfin_read_SICA_SYSCR()         bfin_read32(SICA_SYSCR)
-#define bfin_write_SICA_SYSCR(val)     bfin_write32(SICA_SYSCR, val)
+#define pSICA_SYSCR                    ((uint16_t volatile *)SICA_SYSCR)
+#define bfin_read_SICA_SYSCR()         bfin_read16(SICA_SYSCR)
+#define bfin_write_SICA_SYSCR(val)     bfin_write16(SICA_SYSCR, val)
 #define pSICA_RVECT                    ((uint16_t volatile *)SICA_RVECT)
 #define bfin_read_SICA_RVECT()         bfin_read16(SICA_RVECT)
 #define bfin_write_SICA_RVECT(val)     bfin_write16(SICA_RVECT, val)
@@ -295,9 +295,9 @@
 #define pSICB_SWRST                    ((uint16_t volatile *)SICB_SWRST)
 #define bfin_read_SICB_SWRST()         bfin_read16(SICB_SWRST)
 #define bfin_write_SICB_SWRST(val)     bfin_write16(SICB_SWRST, val)
-#define pSICB_SYSCR                    ((uint32_t volatile *)SICB_SYSCR)
-#define bfin_read_SICB_SYSCR()         bfin_read32(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val)     bfin_write32(SICB_SYSCR, val)
+#define pSICB_SYSCR                    ((uint16_t volatile *)SICB_SYSCR)
+#define bfin_read_SICB_SYSCR()         bfin_read16(SICB_SYSCR)
+#define bfin_write_SICB_SYSCR(val)     bfin_write16(SICB_SYSCR, val)
 #define pSICB_RVECT                    ((uint16_t volatile *)SICB_RVECT)
 #define bfin_read_SICB_RVECT()         bfin_read16(SICB_RVECT)
 #define bfin_write_SICB_RVECT(val)     bfin_write16(SICB_RVECT, val)
diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
index 4c439e5..fde25c0 100644
--- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
+++ b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
@@ -900,9 +900,9 @@
 #define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint32_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR()              bfin_read32(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write32(SYSCR, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
 #define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
 #define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
 #define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
-- 
1.6.2