[U-Boot] [PATCH 19/32] Blackfin: do not program voltage regulator on parts that do not have one

[Mike Frysinger]

Some newer Blackfins (like the BF51x) do not have an on-chip voltage
regulator, so do not attempt to program the memory as if it does.

Signed-off-by: Mike Frysinger <vapier at gentoo.org>
---
 cpu/blackfin/initcode.c |   23 ++++++++++++++++++++---
 1 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index 1352fd6..bbc2fa5 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -203,6 +203,15 @@ static inline void serial_putc(char c)
 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
 #endif
 
+/* some parts do not have an on-chip voltage regulator */
+#if defined(__ADSPBF51x__)
+# define CONFIG_HAS_VR 0
+# undef CONFIG_VR_CTL_VAL
+# define CONFIG_VR_CTL_VAL 0
+#else
+# define CONFIG_HAS_VR 1
+#endif
+
 #ifndef EBIU_RSTCTL
 /* Blackfin with SDRAM */
 #ifndef CONFIG_EBIU_SDBCTL_VAL
@@ -302,15 +311,23 @@ void initcode(ADI_BOOT_DATA *bootstruct)
 		serial_putc('S');
 
 		ADI_SYSCTRL_VALUES memory_settings;
-		memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
+		uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
+		if (CONFIG_HAS_VR) {
+			actions |= SYSCTRL_VRCTL;
+			if (CONFIG_VR_CTL_VAL & FREQ_MASK)
+				actions |= SYSCTRL_INTVOLTAGE;
+			else
+				actions |= SYSCTRL_EXTVOLTAGE;
+			memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
+		} else
+			actions |= SYSCTRL_EXTVOLTAGE;
 		memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
 		memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
 		memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
 #if ANOMALY_05000432
 		bfin_write_SIC_IWR1(0);
 #endif
-		syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT |
-			(CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL);
+		bfrom_SysControl(actions, &memory_settings, NULL);
 #if ANOMALY_05000432
 		bfin_write_SIC_IWR1(-1);
 #endif
-- 
1.6.2