[U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment?
Jon Smirl
jonsmirl at gmail.com
Sun Mar 29 17:21:06 CEST 2009
On Sat, Mar 28, 2009 at 11:26 AM, Markus Rathgeb <maggu2810 at web.de> wrote:
> Hi!
>
> I own a phytec's pcm-030 with the shipped baseboard pcm-973.
> I would like to use a radeon 9200 pci card in the slot on the baseboard.
>
> I have done a git checkout of the u-boot and I am using the 'board
> support patch for phyCORE-MPC5200B-tiny' from the mailing list.
>
> To provide the necessary informations here some outputs the u-boot command line:
>
> =================
> uboot> pci
> Scanning PCI devices on bus 0
> BusDevFun VendorId DeviceId Device Class Sub-Class
> _____________________________________________________________
> 00.18.00 0x1002 0x5c63 Display controller 0x00
> 00.18.01 0x1002 0x5c43 Display controller 0x80
> 00.1a.00 0x1057 0x5809 Bridge device 0x80
>
> uboot> pci header 00.1a.00
> vendor ID = 0x1057
> device ID = 0x5809
> command register = 0x0006
> status register = 0x22a0
> revision ID = 0x00
> class code = 0x06 (Bridge device)
> sub class code = 0x80
> programming interface = 0x00
> cache line = 0x08
> latency time = 0xf8
> header type = 0x00
> BIST = 0x00
> base address 0 = 0xf0000000
> base address 1 = 0x00000008
> base address 2 = 0x00000000
> base address 3 = 0x00000000
> base address 4 = 0x00000000
> base address 5 = 0x00000000
> cardBus CIS pointer = 0x00000000
> sub system vendor ID = 0x0000
> sub system ID = 0x0000
> expansion ROM base address = 0x00000000
> interrupt line = 0x00
> interrupt pin = 0x00
> min Grant = 0x00
> max Latency = 0x00
>
> uboot> pci display 00.1a.00 0 40
> 00000000: 58091057 22a00006 06800000 0000f808
> 00000010: f0000000 00000008 00000000 00000000
> 00000020: 00000000 00000000 00000000 00000000
> 00000030: 00000000 00000000 00000000 00000000
> 00000040: 00000000 00000000 00000000 00000000
> 00000050: 00000000 00000000 00000000 00000000
> 00000060: 00000000 00000000 00000000 00000000
> 00000070: 00000000 00000000 00000000 00000000
> 00000080: 00000000 00000000 00000000 00000000
> 00000090: 00000000 00000000 00000000 00000000
> 000000a0: 00000000 00000000 00000000 00000000
> 000000b0: 00000000 00000000 00000000 00000000
> 000000c0: 00000000 00000000 00000000 00000000
> 000000d0: 00000000 00000000 00000000 00000000
> 000000e0: 00000000 00000000 00000000 00000000
> 000000f0: 00000000 00000000 00000000 00000000
>
> uboot> pci header 00.18.00
> vendor ID = 0x1002
> device ID = 0x5c63
> command register = 0x0007
> status register = 0x0290
> revision ID = 0x01
> class code = 0x03 (Display controller)
> sub class code = 0x00
> programming interface = 0x00
> cache line = 0x08
> latency time = 0x80
> header type = 0x80
> BIST = 0x00
> base address 0 = 0x40000008
> base address 1 = 0x50000001
> base address 2 = 0x44000000
> base address 3 = 0x00000000
> base address 4 = 0x00000000
> base address 5 = 0x00000000
> cardBus CIS pointer = 0x00000000
> sub system vendor ID = 0x0001
> sub system ID = 0x0001
> expansion ROM base address = 0x00000000
> interrupt line = 0xff
> interrupt pin = 0x01
> min Grant = 0x08
> max Latency = 0x00
>
> uboot> pci display 00.18.00 0 40
> 00000000: 5c631002 02900007 03000001 00808008
> 00000010: 40000008 50000001 44000000 00000000
> 00000020: 00000000 00000000 00000000 00010001
> 00000030: 00000000 00000050 00000000 000801ff
> 00000040: 00000000 00000000 00000000 00010001
> 00000050: 06020001 00000000 00205002 4f000210
> 00000060: 00000200 00000000 00000000 00000000
> 00000070: 00000000 00000000 00000000 00000000
> 00000080: 00000005 00000000 00000000 00000000
> 00000090: 00000000 00000000 00000000 00000000
> 000000a0: 00000000 00000000 00000000 00000000
> 000000b0: 00000000 00000000 00000000 00000000
> 000000c0: 00000000 00000000 00000000 00000000
> 000000d0: 00000000 00000000 00000000 00000000
> 000000e0: 00000000 00000000 00000000 00000000
> 000000f0: 00000000 00000000 00000000 00000000
>
> uboot> pci header 00.18.01
> vendor ID = 0x1002
> device ID = 0x5c43
> command register = 0x0006
> status register = 0x0290
> revision ID = 0x01
> class code = 0x03 (Display controller)
> sub class code = 0x80
> programming interface = 0x00
> cache line = 0x08
> latency time = 0x80
> header type = 0x00
> BIST = 0x00
> base address 0 = 0x48000008
> base address 1 = 0x4c000000
> base address 2 = 0x00000000
> base address 3 = 0x00000000
> base address 4 = 0x00000000
> base address 5 = 0x00000000
> cardBus CIS pointer = 0x00000000
> sub system vendor ID = 0x0001
> sub system ID = 0x0000
> expansion ROM base address = 0x00000000
> interrupt line = 0xff
> interrupt pin = 0x00
> min Grant = 0x08
> max Latency = 0x00
>
> uboot> pci display 00.18.01 0 40
> 00000000: 5c431002 02900006 03800001 00008008
> 00000010: 48000008 4c000000 00000000 00000000
> 00000020: 00000000 00000000 00000000 00000001
> 00000030: 00000000 00000050 00000000 000800ff
> 00000040: 00000000 00000000 00000000 00000000
> 00000050: 06020001 00000000 00205002 4f000210
> 00000060: 00000200 00000000 00000000 00000000
> 00000070: 00000000 00000000 00000000 00000000
> 00000080: 00000000 00000000 00000000 00000000
> 00000090: 00000000 00000000 00000000 00000000
> 000000a0: 00000000 00000000 00000000 00000000
> 000000b0: 00000000 00000000 00000000 00000000
> 000000c0: 00000000 00000000 00000000 00000000
> 000000d0: 00000000 00000000 00000000 00000000
> 000000e0: 00000000 00000000 00000000 00000000
> 000000f0: 00000000 00000000 00000000 00000000
> =================
>
> Then I prepared to access the following memory addresses:
>
> 00.1a.00: BAR0, BAR1, BAR2
> uboot> md 0xf0000000 1
> f0000000: 0000f000 ....
> uboot> md 0x00000008 1
> 00000008: 00c43004 ..0.
> uboot> md 0x00000000 1
> 00000000: 12c40044 ...D
>
> 00.18.00: BAR0, BAR1, BAR2
> uboot> md 0x40000008 1
> 40000008: --> hang
> uboot> md 0x50000001 1
> 50000001: 00000000 ....
> uboot> md 0x44000000 1
> 44000000: 00000000 ....
>
> 00.18.00: BAR0, BAR1, BAR2
> uboot> md 0x48000008 1
> 48000008: --> hang
> uboot> md 0x4c000000 1
> 4c000000: 00000000 ....
> uboot> md 0x00000000 1
> 00000000: 12c40044 ...D
>
> But this should be okay, because the card requieres some "BIOS"
> initialization code to be run (i believe).
> See: http://lists.denx.de/pipermail/u-boot/2004-November/007754.html
>
>
> Then I added the following lines to u-boot configuration file for
> phyCORE-MPC5200B-tiny:
>
> #define CONFIG_VIDEO
> #ifdef CONFIG_VIDEO
> #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
> #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
> #define VIDEO_IO_OFFSET CONFIG_PCI_IO_BUS
> #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
> #define CONFIG_VIDEO_SW_CURSOR
> #define CONFIG_VIDEO_LOGO
> #define CONFIG_CFB_CONSOLE
> #define CONFIG_SPLASH_SCREEN
> #define CONFIG_VGA_AS_SINGLE_DEVICE
> #define CONFIG_CMD_BMP
> #endif
>
> (Is VIDEO_IO_OFFSET okay? Is CONFIG_SYS_ISA_IO_BASE_ADDRESS needed?)
>
> When I start the board with that u-boot configuration (I define DEBUG
> in ./video/ati_radeon_fb.c) I get the following messages:
>
> CPU: MPC5200B v2.2, Core v1.4 at 400 MHz
> Bus 133.333 MHz, IPB 133.333 MHz, PCI 33.333 MHz
> Board: phyCORE-MPC5200B-tiny
> I2C: ready
> DRAM: 64 MB
> SP: 0x03e45758
> FLASH: 16 MB
> PCI: Bus Dev VenId DevId Class Int
> 00 18 1002 5c63 0300 ff
> 00 18 1002 5c43 0380 ff
> 00 1a 1057 5809 0680 00
> ATI Radeon video card (1002, 5c63) found @(0:24:0)
> videoboot: Booting PCI video card bus 0, function 0, device 24
> radeonfb: Found 0k of SDRAM 64 bits wide videoram
> Radeon: framebuffer base phy address 0x40000000,MMIO base phy address
> 0x44000000,framebuffer local base 0xfb400000.
> 640x480x8 31kHz 59Hz
> Cursor Start 4004b000 Pattern Start 4004c000
>
> Then the system hangs again.
>
> I prepare to find the line that is responsible and believe it is
> in the file './video/ati_radeon_fb.c'
> in the function 'void *video_hw_init(void)'
> When the video memory will be accessed.
>
> /* Clear video memory (only visible screen area) */
> i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
> vm = (unsigned int *) pGD->pciBase;
> while (i--)
> *vm++ = 0; <-- HERE !!
This is hanging on a write to the PCI bus. Print out the vm pointer
and make sure it is pointing to an area that is mapped into memory.
To investigate further exit the code before trying to write. Use
u-boot commands to then probe the memory and make sure everything is
setup. Running the video BIOS may have reprogrammed the BARs.
I've also noticed that the u-boot code is not setting up the PCI
controller to cause a machine exception on a read/write to an invalid
address. Or maybe the machine check is happening and u-boot is
hanging when it tries to handle it. You may be getting a machine check
on this write, and then u-boot goes off in the weeds trying to process
it.
I don't have a PCI capable baseboard so I can't try this.
>
> So, what can I do?
> Can somebody help me.
>
>
>
>
>
> Something to say about the baseboard from the patch set of the current BSP.
> There is the device tree changed (pcm030.dts) with this comment:
>
> ===========
> The regular shipped PCM-973 baseboard has only processor's IRQ0 routed as
> INT A to the single slot.
>
> This means, the interrupt routing map must be much smaller to get a correct
> behaviour.
>
> The current DTS also contains a second slot definition, that was never present
> on this type of baseboard.
>
> -----------------------------------------------------------------------------
> Attention: The restriction in available interrupt channels prevent the usage
> of multi function PCI devices! Its impossible to use other functions than the
> first one, if the other functions are using INT B...INT D for their interrupt.
> -----------------------------------------------------------------------------
>
> It seems the PCM-973 supports three additional (not soldered) resistors, to
> route the missed INT B... INT D signals to processor's IRQ1...IRQ3. This need
> some help from the manufacturer to find resistor's right locations.
> --> Unresolved yet.
> ===========
>
> But the device tree is not the problem at this step, or am I missing something?
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>
--
Jon Smirl
jonsmirl at gmail.com
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