[U-Boot] [PATCH 08/10] mmc: some endianess fixes for generic mmc subsystem

[Ilya Yanok]

We save response in the cpu order so we need to parse it in the
cpu order too. Things fixed by this patch:
1. OCR_BUSY should be the highest bit in 32-bit response.
2. Proper "tran speed" calculation on LE systems (tran_exp and
   tran_mant should be in 96..98 and 99..102 bits of 128-bit
   response respectively).
3. Proper MMC version detection.

Signed-off-by: Ilya Yanok <yanok at emcraft.com>
---
 drivers/mmc/mmc.c |   10 +++++-----
 include/mmc.h     |    2 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 77a9aea..f7a989b 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -284,7 +284,7 @@ sd_send_op_cond(struct mmc *mmc)
 			return err;
 
 		udelay(1000);
-	} while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
+	} while ((!(((uint *)cmd.response)[0] & OCR_BUSY)) && timeout--);
 
 	if (timeout <= 0)
 		return UNUSABLE_ERR;
@@ -321,7 +321,7 @@ int mmc_send_op_cond(struct mmc *mmc)
 			return err;
 
 		udelay(1000);
-	} while (!(cmd.response[0] & OCR_BUSY) && timeout--);
+	} while (!(((uint *)cmd.response)[0] & OCR_BUSY) && timeout--);
 
 	if (timeout <= 0)
 		return UNUSABLE_ERR;
@@ -651,7 +651,7 @@ int mmc_startup(struct mmc *mmc)
 	mmc->csd[3] = ((uint *)(cmd.response))[3];
 
 	if (mmc->version == MMC_VERSION_UNKNOWN) {
-		int version = (cmd.response[0] >> 2) & 0xf;
+		int version = (mmc->csd[0] >> 26) & 0xf;
 
 		switch (version) {
 			case 0:
@@ -676,8 +676,8 @@ int mmc_startup(struct mmc *mmc)
 	}
 
 	/* divide frequency by 10, since the mults are 10x bigger */
-	freq = fbase[(cmd.response[3] & 0x7)];
-	mult = multipliers[((cmd.response[3] >> 3) & 0xf)];
+	freq = fbase[(mmc->csd[0] & 0x7)];
+	mult = multipliers[((mmc->csd[0] >> 3) & 0xf)];
 
 	mmc->tran_speed = freq * mult;
 
diff --git a/include/mmc.h b/include/mmc.h
index b9b27ba..64764cb 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -91,7 +91,7 @@
 #define MMC_HS_TIMING		0x00000100
 #define MMC_HS_52MHZ		0x2
 
-#define OCR_BUSY	0x80
+#define OCR_BUSY	0x80000000
 #define OCR_HCS		0x40000000
 
 #define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
-- 
1.6.0.6