[U-Boot] MII register display
Jon Smirl
jonsmirl at gmail.com
Thu May 7 03:53:21 CEST 2009
On Wed, May 6, 2009 at 2:57 PM, Jon Smirl <jonsmirl at gmail.com> wrote:
> Why is "speed selection = 10 Mbps" when both sides support 100Mb?
> Is uboot decoding this register correctly?
>
> uboot> mii dump 0 0
> 0. (1000) -- PHY control register --
> (8000:0000) 0.15 = 0 reset
> (4000:0000) 0.14 = 0 loopback
> (2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps
This b00 here is confusing. b is a valid hex character, I thought this
was reporting the register value as 0xb00.
Instead it appears to be trying to indicate that the two bits are binary?
> (1000:1000) 0.12 = 1 A/N enable
> (0800:0000) 0.11 = 0 power-down
> (0400:0000) 0.10 = 0 isolate
> (0200:0000) 0. 9 = 0 restart A/N
> (0100:0000) 0. 8 = 0 duplex = half
> (0080:0000) 0. 7 = 0 collision test enable
> (003f:0000) 0. 5- 0 = 0 (reserved)
>
> Definition from Linux:
>
> /* Basic mode control register. */
> #define BMCR_RESV 0x003f /* Unused... */
> #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
> #define BMCR_CTST 0x0080 /* Collision test */
> #define BMCR_FULLDPLX 0x0100 /* Full duplex */
> #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
> #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
> #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
> #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
> #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
> #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
> #define BMCR_RESET 0x8000 /* Reset the DP83840 */
>
>
>
>
> uboot> mii dump 0 1
> 1. (786d) -- PHY status register --
> (8000:0000) 1.15 = 0 100BASE-T4 able
> (4000:4000) 1.14 = 1 100BASE-X full duplex able
> (2000:2000) 1.13 = 1 100BASE-X half duplex able
> (1000:1000) 1.12 = 1 10 Mbps full duplex able
> (0800:0800) 1.11 = 1 10 Mbps half duplex able
> (0400:0000) 1.10 = 0 100BASE-T2 full duplex able
> (0200:0000) 1. 9 = 0 100BASE-T2 half duplex able
> (0100:0000) 1. 8 = 0 extended status
> (0080:0000) 1. 7 = 0 (reserved)
> (0040:0040) 1. 6 = 1 MF preamble suppression
> (0020:0020) 1. 5 = 1 A/N complete
> (0010:0000) 1. 4 = 0 remote fault
> (0008:0008) 1. 3 = 1 A/N able
> (0004:0004) 1. 2 = 1 link status
> (0002:0000) 1. 1 = 0 jabber detect
> (0001:0001) 1. 0 = 1 extended capabilities
>
>
> uboot> mii dump 0 2
> 2. (0022) -- PHY ID 1 register --
> (ffff:0022) 2.15- 0 = 34 OUI portion
>
>
> uboot> mii dump 0 3
> 3. (161a) -- PHY ID 2 register --
> (fc00:1400) 3.15-10 = 5 OUI portion
> (03f0:0210) 3. 9- 4 = 33 manufacturer part number
> (000f:000a) 3. 3- 0 = 10 manufacturer rev. number
>
>
> uboot> mii dump 0 4
> 4. (01e1) -- Autonegotiation advertisement register --
> (8000:0000) 4.15 = 0 next page able
> (4000:0000) 4.14 = 0 reserved
> (2000:0000) 4.13 = 0 remote fault
> (1000:0000) 4.12 = 0 reserved
> (0800:0000) 4.11 = 0 asymmetric pause
> (0400:0000) 4.10 = 0 pause enable
> (0200:0000) 4. 9 = 0 100BASE-T4 able
> (0100:0100) 4. 8 = 1 100BASE-TX full duplex able
> (0080:0080) 4. 7 = 1 100BASE-TX able
> (0040:0040) 4. 6 = 1 10BASE-T full duplex able
> (0020:0020) 4. 5 = 1 10BASE-T able
> (001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3
>
>
> uboot> mii dump 0 5
> 5. (c5e1) -- Autonegotiation partner abilities register --
> (8000:8000) 5.15 = 1 next page able
> (4000:4000) 5.14 = 1 acknowledge
> (2000:0000) 5.13 = 0 remote fault
> (1000:0000) 5.12 = 0 (reserved)
> (0800:0000) 5.11 = 0 asymmetric pause able
> (0400:0400) 5.10 = 1 pause able
> (0200:0000) 5. 9 = 0 100BASE-T4 able
> (0100:0100) 5. 8 = 1 100BASE-X full duplex able
> (0080:0080) 5. 7 = 1 100BASE-TX able
> (0040:0040) 5. 6 = 1 10BASE-T full duplex able
> (0020:0020) 5. 5 = 1 10BASE-T able
> (001f:0001) 5. 4- 0 = 1 selector = IEEE 802.3
>
>
> uboot>
>
>
> --
> Jon Smirl
> jonsmirl at gmail.com
>
--
Jon Smirl
jonsmirl at gmail.com
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