[U-Boot] [PATCH 26/29] MPC512x FEC: remove duplicated code and data types
Wolfgang Denk
wd at denx.de
Sat May 9 21:51:05 CEST 2009
* Use "u{8,16,32}" instead of "uint{8,16,32}" data types
* Drop use of include/mpc512x.h
Signed-off-by: Wolfgang Denk <wd at denx.de>
Cc: John Rigby <jcrigby at gmail.com>
---
drivers/net/mpc512x_fec.c | 49 +++++-----
drivers/net/mpc512x_fec.h | 253 ++++++++++++++++++++++-----------------------
2 files changed, 148 insertions(+), 154 deletions(-)
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index 8fcced5..10a78ab 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -7,7 +7,6 @@
*/
#include <common.h>
-#include <mpc512x.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
@@ -26,11 +25,11 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#if (DEBUG & 0x40)
-static uint32 local_crc32(char *string, unsigned int crc_value, int len);
+static u32 local_crc32(char *string, unsigned int crc_value, int len);
#endif
-int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
-int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
+int fec512x_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
+int fec512x_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data);
int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
static uchar rx_buff[FEC_BUFFER_SIZE];
@@ -40,9 +39,9 @@ static int rx_buff_idx = 0;
#if (DEBUG & 0x2)
static void mpc512x_fec_phydump (char *devname)
{
- uint16 phyStatus, i;
- uint8 phyAddr = CONFIG_PHY_ADDR;
- uint8 reg_mask[] = {
+ u16 phyStatus, i;
+ u8 phyAddr = CONFIG_PHY_ADDR;
+ u8 reg_mask[] = {
/* regs to print: 0...8, 21,27,31 */
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
@@ -66,7 +65,7 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
* Receive BDs init
*/
for (ix = 0; ix < FEC_RBD_NUM; ix++) {
- fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix];
+ fec->bdBase->rbd[ix].dataPointer = (u32)&fec->bdBase->recv_frames[ix];
fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
fec->bdBase->rbd[ix].dataLength = 0;
}
@@ -164,10 +163,10 @@ static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
/********************************************************************/
static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
{
- uint8 currByte; /* byte for which to compute the CRC */
+ u8 currByte; /* byte for which to compute the CRC */
int byte; /* loop - counter */
int bit; /* loop - counter */
- uint32 crc = 0xffffffff; /* initial value */
+ u32 crc = 0xffffffff; /* initial value */
/*
* The algorithm used is the following:
@@ -252,8 +251,8 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
fec->eth->r_buff_size = FEC_BUFFER_SIZE;
/* Setup BD base addresses */
- fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
- fec->eth->x_des_start = (uint32)fec->bdBase->tbd;
+ fec->eth->r_des_start = (u32)fec->bdBase->rbd;
+ fec->eth->x_des_start = (u32)fec->bdBase->tbd;
/* DMA Control */
fec->eth->dma_control = 0xc0000000;
@@ -277,9 +276,9 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
{
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
- const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
+ const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
int timeout = 1;
- uint16 phyStatus;
+ u16 phyStatus;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_init_phy... Begin\n");
@@ -488,7 +487,7 @@ static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
*/
pTbd = &fec->bdBase->tbd[fec->tbdIndex];
pTbd->dataLength = data_length;
- pTbd->dataPointer = (uint32)eth_data;
+ pTbd->dataPointer = (u32)eth_data;
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
@@ -574,7 +573,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
printf ("recv data length 0x%08x data hdr: ",
pRbd->dataLength);
for (i = 0; i < 14; i++)
- printf ("%x ", *((uint8*)pRbd->dataPointer + i));
+ printf ("%x ", *((u8*)pRbd->dataPointer + i));
printf("\n");
}
#endif
@@ -648,7 +647,7 @@ int mpc512x_fec_initialize (bd_t * bis)
* this pointer is lost, so cannot be freed
*/
bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
- fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
+ fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
/*
@@ -685,13 +684,13 @@ int mpc512x_fec_initialize (bd_t * bis)
/* MII-interface related functions */
/********************************************************************/
-int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
+int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fec512x_t *fec512x = &im->fec;
ethernet_regs *eth = (ethernet_regs *)fec512x;
- uint32 reg; /* convenient holder for the PHY register */
- uint32 phy; /* convenient holder for the PHY */
+ u32 reg; /* convenient holder for the PHY register */
+ u32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
/*
@@ -723,19 +722,19 @@ int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * r
/*
* it's now safe to read the PHY's register
*/
- *retVal = (uint16) eth->mii_data;
+ *retVal = (u16) eth->mii_data;
return 0;
}
/********************************************************************/
-int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
+int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fec512x_t *fec512x = &im->fec;
ethernet_regs *eth = (ethernet_regs *)fec512x;
- uint32 reg; /* convenient holder for the PHY register */
- uint32 phy; /* convenient holder for the PHY */
+ u32 reg; /* convenient holder for the PHY register */
+ u32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
@@ -765,7 +764,7 @@ int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 da
}
#if (DEBUG & 0x40)
-static uint32 local_crc32 (char *string, unsigned int crc_value, int len)
+static u32 local_crc32 (char *string, unsigned int crc_value, int len)
{
int i;
char c;
diff --git a/drivers/net/mpc512x_fec.h b/drivers/net/mpc512x_fec.h
index 9c38502..67c9b64 100644
--- a/drivers/net/mpc512x_fec.h
+++ b/drivers/net/mpc512x_fec.h
@@ -9,11 +9,6 @@
#define __MPC512X_FEC_H
#include <common.h>
-#include <mpc512x.h>
-
-typedef unsigned long uint32;
-typedef unsigned short uint16;
-typedef unsigned char uint8;
typedef struct ethernet_register_set {
@@ -21,135 +16,135 @@ typedef struct ethernet_register_set {
/* Control and status Registers (offset 000-1FF) */
- volatile uint32 fec_id; /* MBAR_ETH + 0x000 */
- volatile uint32 ievent; /* MBAR_ETH + 0x004 */
- volatile uint32 imask; /* MBAR_ETH + 0x008 */
-
- volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */
- volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */
- volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */
-
- volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */
- volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */
-
- volatile uint32 RES2[6]; /* MBAR_ETH + 0x028-03C */
- volatile uint32 mii_data; /* MBAR_ETH + 0x040 */
- volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */
-
- volatile uint32 RES3[7]; /* MBAR_ETH + 0x048-060 */
- volatile uint32 mib_control; /* MBAR_ETH + 0x064 */
-
- volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */
- volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */
- volatile uint32 r_hash; /* MBAR_ETH + 0x088 */
-
- volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */
- volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */
-
- volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */
- volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */
- volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */
- volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */
-
- volatile uint32 RES7[10]; /* MBAR_ETH + 0x0F0-114 */
- volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */
- volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */
- volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */
- volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */
-
- volatile uint32 RES8[6]; /* MBAR_ETH + 0x128-13C */
- volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */
- volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */
- volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */
- volatile uint32 r_bound; /* MBAR_ETH + 0x14C */
- volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */
-
- volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */
- volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */
- volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */
- volatile uint32 r_buff_size; /* MBAR_ETH + 0x188 */
- volatile uint32 RES11[26]; /* MBAR_ETH + 0x18C-1F0 */
- volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */
- volatile uint32 RES12[2]; /* MBAR_ETH + 0x1F8-1FC */
+ volatile u32 fec_id; /* MBAR_ETH + 0x000 */
+ volatile u32 ievent; /* MBAR_ETH + 0x004 */
+ volatile u32 imask; /* MBAR_ETH + 0x008 */
+
+ volatile u32 RES0[1]; /* MBAR_ETH + 0x00C */
+ volatile u32 r_des_active; /* MBAR_ETH + 0x010 */
+ volatile u32 x_des_active; /* MBAR_ETH + 0x014 */
+
+ volatile u32 RES1[3]; /* MBAR_ETH + 0x018-020 */
+ volatile u32 ecntrl; /* MBAR_ETH + 0x024 */
+
+ volatile u32 RES2[6]; /* MBAR_ETH + 0x028-03C */
+ volatile u32 mii_data; /* MBAR_ETH + 0x040 */
+ volatile u32 mii_speed; /* MBAR_ETH + 0x044 */
+
+ volatile u32 RES3[7]; /* MBAR_ETH + 0x048-060 */
+ volatile u32 mib_control; /* MBAR_ETH + 0x064 */
+
+ volatile u32 RES4[7]; /* MBAR_ETH + 0x068-80 */
+ volatile u32 r_cntrl; /* MBAR_ETH + 0x084 */
+ volatile u32 r_hash; /* MBAR_ETH + 0x088 */
+
+ volatile u32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */
+ volatile u32 x_cntrl; /* MBAR_ETH + 0x0C4 */
+
+ volatile u32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */
+ volatile u32 paddr1; /* MBAR_ETH + 0x0E4 */
+ volatile u32 paddr2; /* MBAR_ETH + 0x0E8 */
+ volatile u32 op_pause; /* MBAR_ETH + 0x0EC */
+
+ volatile u32 RES7[10]; /* MBAR_ETH + 0x0F0-114 */
+ volatile u32 iaddr1; /* MBAR_ETH + 0x118 */
+ volatile u32 iaddr2; /* MBAR_ETH + 0x11C */
+ volatile u32 gaddr1; /* MBAR_ETH + 0x120 */
+ volatile u32 gaddr2; /* MBAR_ETH + 0x124 */
+
+ volatile u32 RES8[6]; /* MBAR_ETH + 0x128-13C */
+ volatile u32 fifo_id; /* MBAR_ETH + 0x140 */
+ volatile u32 x_wmrk; /* MBAR_ETH + 0x144 */
+ volatile u32 RES9[1]; /* MBAR_ETH + 0x148 */
+ volatile u32 r_bound; /* MBAR_ETH + 0x14C */
+ volatile u32 r_fstart; /* MBAR_ETH + 0x150 */
+
+ volatile u32 RES10[11]; /* MBAR_ETH + 0x154-17C */
+ volatile u32 r_des_start; /* MBAR_ETH + 0x180 */
+ volatile u32 x_des_start; /* MBAR_ETH + 0x184 */
+ volatile u32 r_buff_size; /* MBAR_ETH + 0x188 */
+ volatile u32 RES11[26]; /* MBAR_ETH + 0x18C-1F0 */
+ volatile u32 dma_control; /* MBAR_ETH + 0x1F4 */
+ volatile u32 RES12[2]; /* MBAR_ETH + 0x1F8-1FC */
/* MIB COUNTERS (Offset 200-2FF) */
- volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */
- volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */
- volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
- volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
- volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */
- volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */
- volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */
- volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */
- volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */
- volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */
- volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */
- volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */
- volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */
- volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */
- volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
- volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
- volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
- volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */
- volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */
- volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
- volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */
- volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */
- volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */
- volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */
- volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */
- volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */
- volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */
- volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */
- volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */
- volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
-
- volatile uint32 RES13[2]; /* MBAR_ETH + 0x278-27C */
- volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */
- volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */
- volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
- volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
- volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */
- volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */
- volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */
- volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */
- volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */
-
- volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
-
- volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */
- volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
- volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
- volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
- volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
- volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
- volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
- volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */
- volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */
- volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
- volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */
- volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */
- volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */
- volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */
- volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
-
- volatile uint32 RES14[6]; /* MBAR_ETH + 0x2E4-2FC */
-
- volatile uint32 RES15[64]; /* MBAR_ETH + 0x300-3FF */
+ volatile u32 rmon_t_drop; /* MBAR_ETH + 0x200 */
+ volatile u32 rmon_t_packets; /* MBAR_ETH + 0x204 */
+ volatile u32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
+ volatile u32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
+ volatile u32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */
+ volatile u32 rmon_t_undersize; /* MBAR_ETH + 0x214 */
+ volatile u32 rmon_t_oversize; /* MBAR_ETH + 0x218 */
+ volatile u32 rmon_t_frag; /* MBAR_ETH + 0x21C */
+ volatile u32 rmon_t_jab; /* MBAR_ETH + 0x220 */
+ volatile u32 rmon_t_col; /* MBAR_ETH + 0x224 */
+ volatile u32 rmon_t_p64; /* MBAR_ETH + 0x228 */
+ volatile u32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */
+ volatile u32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */
+ volatile u32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */
+ volatile u32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
+ volatile u32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
+ volatile u32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
+ volatile u32 rmon_t_octets; /* MBAR_ETH + 0x244 */
+ volatile u32 ieee_t_drop; /* MBAR_ETH + 0x248 */
+ volatile u32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
+ volatile u32 ieee_t_1col; /* MBAR_ETH + 0x250 */
+ volatile u32 ieee_t_mcol; /* MBAR_ETH + 0x254 */
+ volatile u32 ieee_t_def; /* MBAR_ETH + 0x258 */
+ volatile u32 ieee_t_lcol; /* MBAR_ETH + 0x25C */
+ volatile u32 ieee_t_excol; /* MBAR_ETH + 0x260 */
+ volatile u32 ieee_t_macerr; /* MBAR_ETH + 0x264 */
+ volatile u32 ieee_t_cserr; /* MBAR_ETH + 0x268 */
+ volatile u32 ieee_t_sqe; /* MBAR_ETH + 0x26C */
+ volatile u32 t_fdxfc; /* MBAR_ETH + 0x270 */
+ volatile u32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
+
+ volatile u32 RES13[2]; /* MBAR_ETH + 0x278-27C */
+ volatile u32 rmon_r_drop; /* MBAR_ETH + 0x280 */
+ volatile u32 rmon_r_packets; /* MBAR_ETH + 0x284 */
+ volatile u32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
+ volatile u32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
+ volatile u32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */
+ volatile u32 rmon_r_undersize; /* MBAR_ETH + 0x294 */
+ volatile u32 rmon_r_oversize; /* MBAR_ETH + 0x298 */
+ volatile u32 rmon_r_frag; /* MBAR_ETH + 0x29C */
+ volatile u32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */
+
+ volatile u32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
+
+ volatile u32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */
+ volatile u32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
+ volatile u32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
+ volatile u32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
+ volatile u32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
+ volatile u32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
+ volatile u32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
+ volatile u32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */
+ volatile u32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */
+ volatile u32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
+ volatile u32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */
+ volatile u32 ieee_r_align; /* MBAR_ETH + 0x2D4 */
+ volatile u32 r_macerr; /* MBAR_ETH + 0x2D8 */
+ volatile u32 r_fdxfc; /* MBAR_ETH + 0x2DC */
+ volatile u32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
+
+ volatile u32 RES14[6]; /* MBAR_ETH + 0x2E4-2FC */
+
+ volatile u32 RES15[64]; /* MBAR_ETH + 0x300-3FF */
} ethernet_regs;
/* Receive & Transmit Buffer Descriptor definitions */
typedef struct BufferDescriptor {
- uint16 status;
- uint16 dataLength;
- uint32 dataPointer;
+ u16 status;
+ u16 dataLength;
+ u32 dataPointer;
} FEC_RBD;
typedef struct {
- uint16 status;
- uint16 dataLength;
- uint32 dataPointer;
+ u16 status;
+ u16 dataLength;
+ u32 dataPointer;
} FEC_TBD;
/* private structure */
@@ -170,7 +165,7 @@ typedef enum {
#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
typedef struct {
- uint8 frame[FEC_BUFFER_SIZE];
+ u8 frame[FEC_BUFFER_SIZE];
} mpc512x_frame;
typedef struct {
@@ -183,10 +178,10 @@ typedef struct {
ethernet_regs *eth;
xceiver_type xcv_type; /* transceiver type */
mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */
- uint16 rbdIndex; /* next receive BD to read */
- uint16 tbdIndex; /* next transmit BD to send */
- uint16 usedTbdIndex; /* next transmit BD to clean */
- uint16 cleanTbdNum; /* the number of available transmit BDs */
+ u16 rbdIndex; /* next receive BD to read */
+ u16 tbdIndex; /* next transmit BD to send */
+ u16 usedTbdIndex; /* next transmit BD to clean */
+ u16 cleanTbdNum; /* the number of available transmit BDs */
} mpc512x_fec_priv;
/* RBD bits definitions */
--
1.6.0.6
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