[U-Boot] [PATCH 08/29] MPC512x: add support for ARIA board

Heiko Schocher hs at denx.de
Sun May 10 10:36:14 CEST 2009


Hello Wolfgang,


some minor coments ..

Wolfgang Denk wrote:
> ARIA is a MPC5121E based COM Express module by Dave/DENX.
> 
> Signed-off-by: Wolfgang Denk <wd at denx.de>
> Cc: John Rigby <jcrigby at gmail.com>
> ---
[...]
> +#########################################################################
> diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
> new file mode 100644
> index 0000000..24aaf94
> --- /dev/null
> +++ b/board/davedenx/aria/aria.c
> @@ -0,0 +1,418 @@
> +/*
> + * (C) Copyright 2009 Wolfgang Denk <wd at denx.de>
> + * (C) Copyright 2009 Dave Srl www.dave.eu

[...]

> +int board_early_init_f (void)
> +{
> +	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> +	u32 spridr;
> +
> +	/*
> +	 * Initialize Local Window for the On Board FPGA access
> +	 */
> +	out_be32(&im->sysconf.lpcs2aw,
> +		CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
> +		CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
> +	);
> +	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
> +
> +	/*
> +	 * According to MPC5121e RM, configuring local access windows should
> +	 * be followed by a dummy read of the config register that was
> +	 * modified last and an isync
> +	 */
> +	in_be32(&im->sysconf.lpcs2aw);
> +	__asm__ __volatile__ ("isync");
> +
> +	/*
> +	 * Initialize Local Window for the On Board SRAM access
> +	 */
> +	out_be32(&im->sysconf.lpcs6aw,
> +		CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
> +		CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
> +	);
> +	out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
> +
> +	/*
> +	 * According to MPC5121e RM, configuring local access windows should
> +	 * be followed by a dummy read of the config register that was
> +	 * modified last and an isync
> +	 */
> +	in_be32(&im->sysconf.lpcs6aw);
> +	__asm__ __volatile__ ("isync");
> +
> +	/*
> +	 * Configure Flash Speed
> +	 */
> +	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
> +
> +	spridr = in_be32(&im->sysconf.spridr);
> +

no blank line necessary.

> +	if (SVR_MJREV (spridr) >= 2) {
> +		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
> +	}
> +	/*
> +	 * Enable clocks
> +	 */
> +	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
> +	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
> +#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
> +	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
> +#endif
> +
> +	return 0;
> +}
> +
> +phys_size_t initdram (int board_type)
> +{
> +	u32 msize = 0;
> +
> +	msize = fixed_sdram ();
> +

no blank line necessary.

> +	return msize;
> +}
> +
> +/*
> + * fixed sdram init -- the board doesn't use memory modules that have serial presence
> + * detect or similar mechanism for discovery of the DRAM settings
> + */
> +long int fixed_sdram (void)
> +{
> +	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> +	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
> +	u32 msize_log2 = __ilog2 (msize);
> +	u32 i;
> +
> +	/* Initialize IO Control */
> +	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
> +
> +	/* Initialize DDR Local Window */
> +	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
> +	out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
> +
> +	/*
> +	 * According to MPC5121e RM, configuring local access windows should
> +	 * be followed by a dummy read of the config register that was
> +	 * modified last and an isync
> +	 */
> +	in_be32(&im->sysconf.ddrlaw.ar);
> +	__asm__ __volatile__ ("isync");
> +
> +	/* Enable DDR */
> +	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
> +
> +	/* Initialize DDR Priority Manager */
> +	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
> +	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
> +	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
> +	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
> +	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
> +	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
> +	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
> +	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
> +	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
> +	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
> +	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
> +	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
> +	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
> +	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
> +	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
> +	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
> +	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
> +	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
> +	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
> +	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
> +	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
> +	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
> +	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);

too long lines ... but 2 lines would also look ugly ...

> +
> +	/* Initialize MDDRC */
> +	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
> +	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
> +	out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
> +	out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
> +
> +	/* Initialize DDR */
> +	for (i = 0; i < 10; i++)
> +		out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
> +
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
> +	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
> +
> +	/* Start MDDRC */
> +	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
> +	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
> +
> +	return msize;
> +}
> +
> +int misc_init_r(void)
> +{
> +	u32 tmp;
> +	extern int mpc5121_diu_init(void);
> +
> +	/* we use I2C-2 for on-board eeprom */
> +	i2c_set_bus_num(2);
> +
> +	tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
> +	printf("FPGA:  %u-%u.%u.%u\n",
> +		(tmp & 0xFF000000) >> 24,
> +		(tmp & 0x00FF0000) >> 16,
> +		(tmp & 0x0000FF00) >>  8,
> +		 tmp & 0x000000FF
> +	);
> +
> +#ifdef CONFIG_FSL_DIU_FB
> +#if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
> +	mpc5121_diu_init();
> +#endif
> +#endif
> +

no blank line necessary.

> +	return 0;
> +}
> +static  iopin_t ioregs_init[] = {
> +	/*
> +	 * FEC
> +	 */
> +
> +	/* FEC on PSCx_x*/
> +	{
> +		offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
> +		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
> +		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
> +	},
> +	{
> +		offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
> +		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
> +		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
> +	},
> +	{
> +		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
> +		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
> +		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
> +	},
> +
> +	/*
> +	 * DIU
> +	 */
> +	/* FUNC2=DIU CLK */
> +	{
> +		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
> +		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
> +		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
> +	},
> +	/* FUNC2=DIU_HSYNC */
> +	{
> +		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
> +		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
> +		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
> +	},
> +	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
> +	{
> +		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
> +		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
> +		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
> +	},
> +	/*
> +	 * On board SRAM
> +	 */
> +	/* FUNC2=/LPC CS6 */
> +	{
> +		offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
> +		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
> +		IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
> +	},
> +};
> +
> +
> +int checkboard (void)
> +{
> +	puts ("Board: ARIA\n");
> +
> +	/* initialize function mux & slew rate IO inter alia on IO Pins  */
> +

no blank line necessary

> +	iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));

line too long

> +
> +	return 0;
> +}
> +
> +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
> +void ft_board_setup(void *blob, bd_t *bd)
> +{
> +	ft_cpu_setup(blob, bd);
> +	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
> +}
> +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
> +
> +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
> +
> +void init_ide_reset (void)
> +{
> +	debug ("init_ide_reset\n");
> +
> +	/*
> +	 * Clear the reset bit to reset the interface
> +	 * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
> +	 */
> +	ide_set_reset(1);
> +
> +	/* Assert the reset bit to enable the interface */
> +	ide_set_reset(0);
> +

no blank line necessary

> +}
> +
> +void ide_set_reset (int idereset)
> +{
> +	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> +	debug ("ide_set_reset(%d)\n", idereset);
> +
> +	if (idereset) {
> +		out_be32(&im->pata.pata_ata_control, 0);
> +	} else {
> +		out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
> +	}
> +	udelay(100);
> +}
> +
> +#define CALC_TIMING(t) (t + period - 1) / period
> +
> +int ide_preinit (void)
> +{
> +	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> +	long t;
> +	const struct {
> +		short t0;
> +		short t1;
> +		short t2_8;
> +		short t2_16;
> +		short t2i;
> +		short t4;
> +		short t9;
> +		short tA;
> +	} pio_specs = {

Is this a processor specific register? If so, shouldn;t this go in
include/asm-ppc/immap_512x.h?

> +		.t0    = 600,
> +		.t1    =  70,
> +		.t2_8  = 290,
> +		.t2_16 = 165,
> +		.t2i   =   0,
> +		.t4    =  30,
> +		.t9    =  20,
> +		.tA    =  50,
> +	};
> +	union {
> +		u32 config;
> +		struct {
> +			u8 field1;
> +			u8 field2;
> +			u8 field3;
> +			u8 field4;
> +		}bytes;
> +	}cfg;
> +
> +	debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
> +		in_be32(&im->pata));
> +
> +	/* Set the reset bit to 1 to enable the interface */
> +	ide_set_reset(0);
> +
> +	/* Init timings : we use PIO mode 0 timings */
> +	t = 1000000000 / gd->ips_clk;	/* period in ns */
> +	cfg.bytes.field1 = 3;
> +	cfg.bytes.field2 = 3;
> +	cfg.bytes.field3 = (pio_specs.t1 + t) / t;
> +	cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
> +
> +	out_be32(&im->pata.pata_time1, cfg.config);
> +
> +	cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
> +	cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
> +	cfg.bytes.field3 = 1;
> +	cfg.bytes.field4 = (pio_specs.t4 + t) / t;
> +
> +	out_be32(&im->pata.pata_time2, cfg.config);
> +
> +	cfg.config = in_be32(&im->pata.pata_time3);
> +	cfg.bytes.field1 = (pio_specs.t9 + t) / t;
> +
> +	out_be32(&im->pata.pata_time3, cfg.config);
> +
> +	debug ("PATA preinit complete.\n");
> +
> +	return 0;
> +}
> +
> +#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
> diff --git a/board/davedenx/aria/config.mk b/board/davedenx/aria/config.mk
> new file mode 100644
> index 0000000..838a018
> --- /dev/null
> +++ b/board/davedenx/aria/config.mk
> @@ -0,0 +1,23 @@
> +#
> +# (C) Copyright 2009 Wolfgang Denk <wd at denx.de>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +TEXT_BASE  =   0xFFF00000
> diff --git a/include/configs/aria.h b/include/configs/aria.h
> new file mode 100644
> index 0000000..d335a52
> --- /dev/null
> +++ b/include/configs/aria.h
> @@ -0,0 +1,543 @@
> +/*
> + * (C) Copyright 2009 Wolfgang Denk <wd at denx.de>
> + * (C) Copyright 2009, DAVE Srl <www.dave.eu>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * Aria board configuration file
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_ARIA 1
> +/*
> + * Memory map for the ARIA board:
> + *
> + * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
> + * 0x3000_0000 - 0x3001_FFFF	On Chip SRAM (128 KB)
> + * 0x3010_0000 - 0x3003_FFFF	On Board SRAM (128 KB - max 512KB - 1MB reserved) - CS6

line too long.

> + * 0x3020_0000 - 0x3021_FFFF	FPGA (128 KB) - CS2
> + * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
> + * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
> + * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
> + * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
> + * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
> + */
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_E300		1	/* E300 Family */
> +#define CONFIG_MPC512X		1	/* MPC512X family */
> +#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
> +#define CONFIG_FSL_DIU_LOGO_BMP	1	/* Don't include FSL DIU binary bmp */

here too.

> +
> +/* video */
> +#undef CONFIG_VIDEO
> +
> +#if defined(CONFIG_VIDEO)
> +#define CONFIG_CFB_CONSOLE
> +#define CONFIG_VGA_AS_SINGLE_DEVICE
> +#endif
> +
> +/* CONFIG_PCI is defined at config time */
> +
> +#define CONFIG_SYS_MPC512X_CLKIN	33000000	/* in Hz */
> +
> +#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
> +#define CONFIG_MISC_INIT_R
> +
> +#define CONFIG_SYS_IMMR		0x80000000
> +#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
> +
> +#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
> +#define CONFIG_SYS_MEMTEST_END		0x00400000
> +
> +/*
> + * DDR Setup - manually set all parameters as there's no SPD etc.
> + */
> +#define CONFIG_SYS_DDR_SIZE		256		/* MB */
> +#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
> +#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
> +
> +/* DDR Controller Configuration
> + *
> + * SYS_CFG:
> + *	[31:31]	MDDRC Soft Reset:	Diabled
> + *	[30:30]	DRAM CKE pin:		Enabled
> + *	[29:29]	DRAM CLK:		Enabled
> + *	[28:28]	Command Mode:		Enabled (For initialization only)
> + *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
> + *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
> + *	[20:19]	Read Test:		DON'T USE
> + *	[18:18]	Self Refresh:		Enabled
> + *	[17:17]	16bit Mode:		Disabled
> + *	[16:13] Ready Delay:		2
> + *	[12:12]	Half DQS Delay:		Disabled
> + *	[11:11]	Quarter DQS Delay:	Disabled
> + *	[10:08]	Write Delay:		2
> + *	[07:07]	Early ODT:		Disabled
> + *	[06:06]	On DIE Termination:	Disabled
> + *	[05:05]	FIFO Overflow Clear:	DON'T USE here
> + *	[04:04]	FIFO Underflow Clear:	DON'T USE here
> + *	[03:03]	FIFO Overflow Pending:	DON'T USE here
> + *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
> + *	[01:01]	FIFO Overlfow Enabled:	Enabled
> + *	[00:00]	FIFO Underflow Enabled:	Enabled
> + * TIME_CFG0
> + *	[31:16]	DRAM Refresh Time:	0 CSB clocks
> + *	[15:8]	DRAM Command Time:	0 CSB clocks
> + *	[07:00]	DRAM Precharge Time:	0 CSB clocks
> + * TIME_CFG1
> + *	[31:26]	DRAM tRFC:
> + *	[25:21]	DRAM tWR1:
> + *	[20:17]	DRAM tWRT1:
> + *	[16:11]	DRAM tDRR:
> + *	[10:05]	DRAM tRC:
> + *	[04:00]	DRAM tRAS:
> + * TIME_CFG2
> + *	[31:28]	DRAM tRCD:
> + *	[27:23]	DRAM tFAW:
> + *	[22:19]	DRAM tRTW1:
> + *	[18:15]	DRAM tCCD:
> + *	[14:10] DRAM tRTP:
> + *	[09:05]	DRAM tRP:
> + *	[04:00] DRAM tRPA
> + */
> +#define CONFIG_SYS_MDDRC_SYS_CFG	0xF8604A00
> +#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	0xE8604A00
> +//#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
> +  #define CONFIG_SYS_MDDRC_TIME_CFG1	0x55D81189
> +//#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
> +  #define CONFIG_SYS_MDDRC_TIME_CFG2	0x34790863
> +
> +#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
> +#define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
> +//#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x06183D2E
> +#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x030C3D2E
> +
> +#define CONFIG_SYS_MICRON_NOP		0x01380000
> +#define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
> +#define CONFIG_SYS_MICRON_EM2		0x01020000
> +#define CONFIG_SYS_MICRON_EM3		0x01030000
> +#define CONFIG_SYS_MICRON_EN_DLL	0x01010000
> +#define CONFIG_SYS_MICRON_RFSH		0x01080000
> +#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
> +#define CONFIG_SYS_MICRON_OCD_DEFAULT	0x01010780
> +
> +/* DDR Priority Manager Configuration */
> +#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
> +#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
> +#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
> +#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
> +#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
> +#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
> +#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
> +#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
> +#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
> +#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
> +#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
> +#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
> +#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
> +#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
> +#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
> +#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
> +#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
> +#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
> +#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
> +#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
> +#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
> +#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
> +#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
> +
> +/*
> + * NOR FLASH on the Local Bus
> + */
> +#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */

line too long.

> +#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
> +#define CONFIG_SYS_FLASH_BASE		0xF8000000	/* start of FLASH   */
> +#define CONFIG_SYS_FLASH_SIZE		0x8000000	/* max flash size in bytes */
> +
> +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
> +#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
> +#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
> +#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* max sectors per device */
> +
> +#undef CONFIG_SYS_FLASH_CHECKSUM
> +
> +#define CONFIG_SYS_SRAM_BASE		0x30000000
> +#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
> +
> +#define CONFIG_SYS_ARIA_SRAM_BASE		0x30020000
> +#define CONFIG_SYS_ARIA_SRAM_SIZE		0x20000	/* 128 KB */
> +
> +#define CONFIG_SYS_ARIA_FPGA_BASE		(CONFIG_SYS_ARIA_SRAM_BASE + CONFIG_SYS_ARIA_SRAM_SIZE)

line too long

> +#define CONFIG_SYS_ARIA_FPGA_SIZE		0x20000	/* 128 KB */
> +
> +#define CONFIG_SYS_CS0_CFG		0x05059150
> +#define CONFIG_SYS_CS2_CFG		(	(5 << 24) | \
> +									(5 << 16) | \
> +									(1 << 15) | \
> +									(0 << 14) | \
> +									(0 << 13) | \
> +									(1 << 12) | \
> +									(0 << 10) | \
> +									(3 <<  8) | /* 32 bit */ \
> +									(0 <<  7) | \
> +									(1 <<  6) | \
> +									(1 <<  4) | \
> +									(0 <<  3) | \
> +									(0 <<  2) | \
> +									(0 <<  1) | \
> +									(0 <<  0)   \

Hmm... seems to my, there are some tabs too much here ...

> +								)
> +#define CONFIG_SYS_CS6_CFG		0x05059150
> +#define CONFIG_SYS_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */

line too long

> +
> +/* Use SRAM for initial stack */
> +#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
> +#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE		/* End of used area in RAM */

here too

> +
> +#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
> +#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
> +
> +#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
> +#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
> +#ifdef	CONFIG_FSL_DIU_FB
> +#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
> +#else
> +#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
> +#endif
> +
> +/* FPGA */
> +#define CONFIG_ARIA_FPGA	1
> +
> +
> +/*
> + * Serial Port
> + */
> +#define CONFIG_CONS_INDEX     1
> +#undef CONFIG_SERIAL_SOFTWARE_FIFO
> +
> +/*
> + * Serial console configuration
> + */
> +#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
> +#if CONFIG_PSC_CONSOLE != 3
> +#error CONFIG_PSC_CONSOLE must be 3
> +#endif
> +#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
> +#define CONFIG_SYS_BAUDRATE_TABLE  \
> +	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
> +
> +#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
> +#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
> +#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
> +#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
> +
> +#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
> +/* Use the HUSH parser */
> +#define CONFIG_SYS_HUSH_PARSER
> +#ifdef  CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#endif
> +
> +/*
> + * PCI
> + */
> +#ifdef CONFIG_PCI
> +
> +/*
> + * General PCI
> + */
> +#define CONFIG_SYS_PCI_MEM_BASE	0xA0000000
> +#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
> +#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
> +#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
> +#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
> +#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
> +#define CONFIG_SYS_PCI_IO_BASE		0x00000000
> +#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
> +#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
> +
> +
> +#define CONFIG_PCI_PNP			/* do pci plug-and-play */
> +
> +#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
> +
> +#endif
> +
> +/* I2C */
> +#define CONFIG_HARD_I2C			/* I2C with hardware support */
> +#undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
> +#define CONFIG_I2C_MULTI_BUS
> +#define CONFIG_I2C_CMD_TREE
> +#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
> +#define CONFIG_SYS_I2C_SLAVE		0x7F
> +#if 0
> +#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
> +#endif
> +
> +/*
> + * IIM - IC Identification Module
> + */
> +#undef CONFIG_IIM
> +
> +/*
> + * EEPROM configuration
> + */
> +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
> +#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */

long lines

> +
> +/*
> + * Ethernet configuration
> + */
> +#define CONFIG_MPC512x_FEC	1
> +#define CONFIG_NET_MULTI
> +#define CONFIG_PHY_ADDR		0x17
> +#define CONFIG_MII		1	/* MII PHY management		*/
> +#define CONFIG_FEC_AN_TIMEOUT	1
> +#define CONFIG_HAS_ETH0
> +
> +/*
> + * Environment
> + */
> +#define CONFIG_ENV_IS_IN_FLASH	1
> +/* This has to be a multiple of the Flash sector size */
> +#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)

line too long ... Hmm.. shouldn;t we accept such long lines? It seems
better to me to have such long lines, because it would look uglier if
we split this in two or more lines?

> +#define CONFIG_ENV_SIZE		0x2000
> +#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (256K) for env */
> +
> +/* Address and size of Redundant Environment Sector	*/
> +#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
> +#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
> +
> +#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
> +#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
> +
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_ASKENV
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NFS
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_REGINFO
> +#define CONFIG_CMD_EEPROM
> +#undef CONFIG_CMD_FUSE
> +#undef CONFIG_CMD_IDE
> +#undef CONFIG_CMD_EXT2
> +
> +#if defined(CONFIG_PCI)
> +#define CONFIG_CMD_PCI
> +#endif
> +
> +#if defined(CONFIG_CMD_IDE)
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_MAC_PARTITION
> +#define CONFIG_ISO_PARTITION
> +#endif /* defined(CONFIG_CMD_IDE) */
> +
> +/*
> + * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
> + * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
> + * to 0xFFFF, watchdog timeouts after about 64s. For details refer
> + * to chapter 36 of the MPC5121e Reference Manual.
> + */
> +/* #define CONFIG_WATCHDOG */		/* enable watchdog */
> +#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
> +
> + /*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP			/* undef to save memory */
> +#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
> +#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
> +
> +#ifdef CONFIG_CMD_KGDB
> +	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
> +#else
> +	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
> +#endif
> +
> +
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
> +#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
> +#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */

long lines.

> +
> +/*
> + * For booting Linux, the board info and command line data
> + * have to be in the first 8 MB of memory, since this is
> + * the maximum mapped by the Linux kernel during initialization.
> + */

[...]

bye
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


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