[U-Boot] DDR2 configuration in MPC85xx

[Werner Nedel]

Hi,

I'm working on a mpc85xx board very similar to MPC8548CDS. I have 2 DIMMs
and each one with it own spd eeprom and with only one chip select (cs0 and
cs2). I'm trying to use two 1Gb DDR2s. My ddr configurations:

/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM        /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_DDR_DLL            /* possible DLL fix needed */

#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER    /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE    0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000    /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS        2
#define CONFIG_DIMM_SLOTS_PER_CTLR        1
#define CONFIG_CHIP_SELECTS_PER_CTRL    1

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
#define SPD_EEPROM_ADDRESS2    0x53    /* CTLR 0 DIMM 1 */


Also, I'd changed my ddr.c as follow:

    for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
        if (ctrl_num == 0)
            get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS1);
        if (ctrl_num == 1)
            get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS2);
    }

and removing the ctrl_num checks that avoid ctrl_num = 1 access (in ddr.c
and ddr-gen2.c). My board hangs after initialize the DDR:

I2C:   ready
DRAM:  Initializing
4294963200M left unmapped
DDR:  2 GB

The tlb settings looks fine (debbug in setup_ddr_tlbs()):

ram_tlb_address: 0x0, ram_tlb_address: 0x0, ram_tlb_index: 0x8, tlb_size:
0xa
ram_tlb_address: 0x40000000, ram_tlb_address: 0x40000000, ram_tlb_index:
0x9, tlb_size: 0xa

Am I missing some configuration?

Thanks in advance,

Werner Nedel.