[U-Boot] DDR2 configuration in MPC85xx

[Werner Nedel]

Interesting. I've tried to use your patch but still hanging board_init_f.
Even putting BOOKE_PAGESZ_256M in set_tlb the problem occur.

On Thu, May 14, 2009 at 2:49 PM, Fredrik Arnerup <
fredrik.arnerup at edgeware.tv> wrote:

> > The tlb settings looks fine (debbug in setup_ddr_tlbs()):
> >
> > ram_tlb_address: 0x0, ram_tlb_address: 0x0, ram_tlb_index: 0x8, tlb_size:
> 0xa
> > ram_tlb_address: 0x40000000, ram_tlb_address: 0x40000000, ram_tlb_index:
> 0x9, tlb_size: 0xa
>
> "tlb_size: 0xa" is _not_ fine.
>
> Quoting the 8540 reference manual:
>
> "Translation size. Defines the TLB entry page size. For arrays that contain
> fixed-size TLB entries, TSIZE
> is ignored. For variable page size arrays, the page size is 4^TSIZE Kbytes.
> Note that although the
> Freescale Semiconductor Book E standard supports all 16 page sizes defined
> in Book E, the e500
> supports only the following:
> 0001 4 Kbyte
> 0010 16 Kbyte
> 0011 64 Kbyte
> 0100 256 Kbyte
> 0101 1 Mbyte
> 0110 4 Mbyte
> 0111 16 Mbyte
> 1000 64 Mbyte
> 1001 256 Mbyte"
>
> See my patch for this in "PATCH: bugfix for reading maximum TLB size on
> mpc85xx"
>
> /Fredrik Arnerup
>
>