[U-Boot] [PATCH 2/2] KB9202: Add NAND support
Matthias Kaehlcke
matthias at kaehlcke.net
Sat May 16 00:15:44 CEST 2009
KB9202: Add NAND support
This is a forward port of the patch submitted by Christian from
Kwikbyte in 06/2007
(http://lists.denx.de/pipermail/u-boot/2007-June/022068.html)
Signed-off-by: Matthias Kaehlcke <matthias at kaehlcke.net>
--
--- u-boot-2009.03.org/board/kb9202/Makefile 2009-03-21 22:04:41.000000000 +0100
+++ u-boot-2009.03/board/kb9202/Makefile 2009-05-15 23:30:11.000000000 +0200
@@ -28,7 +28,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS := kb9202.o
+COBJS := kb9202.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null 2009-05-14 23:36:38.280017984 +0200
+++ u-boot-2009.03/board/kb9202/nand.c 2009-05-15 23:30:11.000000000 +0200
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2006 KwikByte kb9200_dev at kwikbyte.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/AT91RM9200.h>
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_CMD_NAND
+
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+
+#define MASK_ALE (1 << 22) /* our ALE is A22 */
+#define MASK_CLE (1 << 21) /* our CLE is A21 */
+
+#ifndef CONFIG_KB9202B_ATL
+#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */
+#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */
+#else
+#define KB9202_NAND_NCE (1 << 26) /* EN* on PB26 */
+#define KB9202_NAND_BUSY (1 << 27) /* RB* on PB27 */
+#endif
+
+/*
+ * Board-specific function to access device control signals
+ */
+static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+ /* clear ALE and CLE bits */
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (ctrl & NAND_NCE)
+ AT91C_BASE_PIOC->PIO_CODR = KB9202_NAND_NCE;
+ else
+ AT91C_BASE_PIOC->PIO_SODR = KB9202_NAND_NCE;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+
+/*
+ * Board-specific function to access the device ready signal.
+ */
+static int kb9202_nand_ready(struct mtd_info *mtd)
+{
+ return (((AT91C_BASE_PIOC->PIO_PDSR) & KB9202_NAND_BUSY) != 0);
+}
+
+
+/*
+ * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference.
+ *
+ * struct nand_chip - NAND Private Flash Chip Data
+ * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
+ * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
+ * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
+ * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
+ * If set to NULL no access to ready/busy is available and the ready/busy information
+ * is read from the chip status register
+ * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
+ * be provided if a hardware ECC is available
+ * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
+ * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
+ * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
+ * special functionality. See the defines for further explanation
+*/
+/*
+ * This routine initializes controller and GPIOs.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+ unsigned value;
+
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->options &= ~(NAND_BUSWIDTH_16);
+ nand->cmd_ctrl = kb9202_nand_hwcontrol;
+ nand->dev_ready = kb9202_nand_ready;
+
+ /* in case running outside of bootloader */
+ AT91C_BASE_PMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_PIOC);
+#ifdef CONFIG_KB9202B_ATL
+ AT91C_BASE_PMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_PIOB);
+#endif
+
+ /* setup nand flash access (allow ample margin) */
+ /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
+ ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[3] =
+ AT91C_SMC2_WSEN |
+ (4 & AT91C_SMC2_NWS) |
+ ((1 << 8) & AT91C_SMC2_TDF) |
+ AT91C_SMC2_DBW_8 |
+ ((1 << 24) & AT91C_SMC2_RWSETUP) |
+ ((1 << 29) & AT91C_SMC2_RWHOLD);
+
+ /* enable internal NAND controller */
+ value = *(AT91C_EBI_CSA);
+ value |= AT91C_EBI_CS3A_SMC_SmartMedia;
+ *(AT91C_EBI_CSA) = value;
+
+ /* enable SMOE/SMWE */
+ AT91C_BASE_PIOC->PIO_ASR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+ AT91C_BASE_PIOC->PIO_PDR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+ AT91C_BASE_PIOC->PIO_OER = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+
+ /* set NCE to high */
+ AT91C_BASE_PIOC->PIO_SODR = KB9202_NAND_NCE;
+
+ /* disable output on pin connected to the busy line of the NAND */
+ AT91C_BASE_PIOC->PIO_ODR = KB9202_NAND_BUSY;
+
+ /* enable the PIO to control NCE and BUSY */
+ AT91C_BASE_PIOC->PIO_PER = KB9202_NAND_NCE | KB9202_NAND_BUSY;
+
+ /* enable output for NCE */
+ AT91C_BASE_PIOC->PIO_OER = KB9202_NAND_NCE;
+
+ return (0);
+}
+
+#endif /* CONFIG_CMD_NAND */
--- u-boot-2009.03.org/include/configs/kb9202.h 2009-05-15 23:31:55.000000000 +0200
+++ u-boot-2009.03/include/configs/kb9202.h 2009-05-15 23:30:11.000000000 +0200
@@ -62,6 +62,11 @@
#ifdef CONFIG_KB9202B
#define CONFIG_BOOTARGS "console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M"
#define CONFIG_BOOTCOMMAND "bootm 0x10000000"
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_CMDLINE
#endif
@@ -71,7 +76,7 @@
/*
* Size of malloc() pool
*/
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_SYS_MALLOC_LEN (1024*1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200
@@ -111,6 +116,9 @@
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
+#ifdef CONFIG_KB9202B
+#define CONFIG_CMD_NAND
+#endif
#define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_BDI
@@ -140,7 +148,11 @@
#define PHYS_FLASH_SIZE 0x200000
#endif
+#ifdef CONFIG_KB9202B_ATL
+#define CFG_MAX_FLASH_BANKS 0
+#else
#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#endif
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_HARD_I2C
--
Matthias Kaehlcke
Embedded Linux Engineer
Barcelona
El trabajo es el refugio de los que no tienen nada que hacer
(Oscar Wilde)
.''`.
using free software / Debian GNU/Linux | http://debian.org : :' :
`. `'`
gpg --keyserver pgp.mit.edu --recv-keys 47D8E5D4 `-
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