[U-Boot] [PATCH] DaVinci Network Driver Updates

[Paulraj, Sandeep]

 Ben,
     Any comments on this patch?

Thanks,
Sandeep

> -----Original Message-----
> From: Paulraj, Sandeep 
> Sent: Tuesday, May 12, 2009 11:46 AM
> To: u-boot at lists.denx.de
> Cc: Paulraj, Sandeep
> Subject: [PATCH] DaVinci Network Driver Updates
> 
> Different flavours of DaVinci SOC's have differences in their EMAC IP
> This patch does the following
> 1) Updates base addresses for DM365
> 2) Updates MDIO frequencies for DM365 and DM646x
> 3) Update EMAC wrapper registers for DM365 and DM646x
> 
> Patch applies to u-boot-net git. the EMAC driver itself 
> will be updated shortly to add support for DM365 and DM646x
> 
> Signed-off-by: Sandeep Paulraj <s-paulraj at ti.com>
> ---
>  include/asm-arm/arch-davinci/emac_defs.h |   32 
> +++++++++++++++++++++++++++++-
>  1 files changed, 31 insertions(+), 1 deletions(-)
> 
> diff --git a/include/asm-arm/arch-davinci/emac_defs.h 
> b/include/asm-arm/arch-davinci/emac_defs.h
> index c11161f..ae75f84 100644
> --- a/include/asm-arm/arch-davinci/emac_defs.h
> +++ b/include/asm-arm/arch-davinci/emac_defs.h
> @@ -38,15 +38,38 @@
>  
>  #include <asm/arch/hardware.h>
>  
> +#ifdef CONFIG_SOC_DM365
> +#define EMAC_BASE_ADDR			(0x01d07000)
> +#define EMAC_WRAPPER_BASE_ADDR		(0x01d0a000)
> +#define EMAC_WRAPPER_RAM_ADDR		(0x01d08000)
> +#define EMAC_MDIO_BASE_ADDR		(0x01d0b000)
> +#else
>  #define EMAC_BASE_ADDR			(0x01c80000)
>  #define EMAC_WRAPPER_BASE_ADDR		(0x01c81000)
>  #define EMAC_WRAPPER_RAM_ADDR		(0x01c82000)
>  #define EMAC_MDIO_BASE_ADDR		(0x01c84000)
> +#endif
>  
> +#ifdef CONFIG_SOC_DM646x
> +/* MDIO module input frequency */
> +#define EMAC_MDIO_BUS_FREQ		76500000
> +/* MDIO clock output frequency */
> +#define EMAC_MDIO_CLOCK_FREQ		2500000		/* 2.5 MHz */
> +#elif defined(CONFIG_SOC_DM365)
> +/* MDIO module input frequency */
> +#define EMAC_MDIO_BUS_FREQ		121500000
> +/* MDIO clock output frequency */
> +#define EMAC_MDIO_CLOCK_FREQ		2200000		/* 2.2 MHz */
> +#else
>  /* MDIO module input frequency */
>  #define EMAC_MDIO_BUS_FREQ		99000000	/* 
> PLL/6 - 99 MHz */
>  /* MDIO clock output frequency */
>  #define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
> +#endif
> +
> +/* PHY mask - set only those phy number bits where phy 
> is/can be connected */
> +#define EMAC_MDIO_PHY_NUM           1
> +#define EMAC_MDIO_PHY_MASK          (1 << EMAC_MDIO_PHY_NUM)
>  
>  /* Ethernet Min/Max packet size */
>  #define EMAC_MIN_ETHERNET_PKT_SIZE	60
> @@ -103,6 +126,8 @@ typedef volatile struct _emac_desc
>  
>  #define EMAC_MACCONTROL_MIIEN_ENABLE		(0x20)
>  #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	(0x1)
> +#define EMAC_MACCONTROL_GIGABIT_ENABLE		(1 << 7)
> +#define EMAC_MACCONTROL_GIGFORCE		(1 << 17)
>  
>  #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE	(0x200000)
>  #define EMAC_RXMBPENABLE_RXBROADEN	(0x2000)
> @@ -258,12 +283,17 @@ typedef struct  {
>  
>  /* EMAC Wrapper Registers Structure */
>  typedef struct  {
> +#if defined(CONFIG_SOC_DM646x) || defined(CONFIG_SOC_DM365)
> +	dv_reg		IDVER;
> +	dv_reg		SOFTRST;
> +	dv_reg		EMCTRL;
> +#else
>  	u_int8_t	RSVD0[4100];
>  	dv_reg		EWCTL;
>  	dv_reg		EWINTTCNT;
> +#endif
>  } ewrap_regs;
>  
> -
>  /* EMAC MDIO Registers Structure */
>  typedef struct  {
>  	dv_reg		VERSION;
> -- 
> 1.6.0.4
> 
>