[U-Boot] [PATCH 11/15] MPC85xx: update uec to support up to 8 UECs in QE

[Haiying Wang]

Signed-off-by: Haiying Wang <Haiying.Wang at freescale.com>
---
 cpu/mpc85xx/cpu.c |    6 +++++
 cpu/mpc85xx/fdt.c |    4 ++-
 drivers/qe/uec.c  |   66 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 74 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index b812d88..eb2aeec 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -399,6 +399,12 @@ int cpu_eth_init(bd_t *bis)
 #if defined(CONFIG_UEC_ETH6)
 	uec_initialize(5);
 #endif
+#if defined(CONFIG_UEC_ETH7)
+	uec_initialize(6);
+#endif
+#if defined(CONFIG_UEC_ETH8)
+	uec_initialize(7);
+#endif
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
 	tsec_standard_init(bis);
 #endif
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 26a8f48..720c645 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -279,7 +279,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 		fdt_fixup_crypto_node(blob, 0);
 
 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
-    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
+    defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) ||\
+    defined(CONFIG_HAS_ETH6) || defined(CONFIG_HAS_ETH7)
 	fdt_fixup_ethernet(blob);
 
 	fdt_add_enet_stashing(blob);
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index eadcc2c..deeb947 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -199,8 +199,64 @@ static uec_info_t eth6_uec_info = {
 	.enet_interface		= CONFIG_SYS_UEC6_INTERFACE_MODE,
 };
 #endif
+#ifdef CONFIG_UEC_ETH7
+static uec_info_t eth7_uec_info = {
+	.uf_info		= {
+		.ucc_num	= CONFIG_SYS_UEC7_UCC_NUM,
+		.rx_clock	= CONFIG_SYS_UEC7_RX_CLK,
+		.tx_clock	= CONFIG_SYS_UEC7_TX_CLK,
+		.eth_type	= CONFIG_SYS_UEC7_ETH_TYPE,
+	},
+#if (CONFIG_SYS_UEC7_ETH_TYPE == FAST_ETH)
+	.num_threads_tx		= UEC_NUM_OF_THREADS_1,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_1,
+#else
+	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
+#endif
+#if (MAX_QE_RISC == 4)
+	.riscTx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.riscRx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
+	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
+	.tx_bd_ring_len		= 16,
+	.rx_bd_ring_len		= 16,
+	.phy_address		= CONFIG_SYS_UEC7_PHY_ADDR,
+	.enet_interface		= CONFIG_SYS_UEC7_INTERFACE_MODE,
+};
+#endif
+#ifdef CONFIG_UEC_ETH8
+static uec_info_t eth8_uec_info = {
+	.uf_info		= {
+		.ucc_num	= CONFIG_SYS_UEC8_UCC_NUM,
+		.rx_clock	= CONFIG_SYS_UEC8_RX_CLK,
+		.tx_clock	= CONFIG_SYS_UEC8_TX_CLK,
+		.eth_type	= CONFIG_SYS_UEC8_ETH_TYPE,
+	},
+#if (CONFIG_SYS_UEC8_ETH_TYPE == FAST_ETH)
+	.num_threads_tx		= UEC_NUM_OF_THREADS_1,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_1,
+#else
+	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
+#endif
+#if (MAX_QE_RISC == 4)
+	.riscTx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.riscRx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
+	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
+	.tx_bd_ring_len		= 16,
+	.rx_bd_ring_len		= 16,
+	.phy_address		= CONFIG_SYS_UEC8_PHY_ADDR,
+	.enet_interface		= CONFIG_SYS_UEC8_INTERFACE_MODE,
+};
+#endif
 
-#define MAXCONTROLLERS	(6)
+#define MAXCONTROLLERS	(8)
 
 static struct eth_device *devlist[MAXCONTROLLERS];
 
@@ -1493,6 +1549,14 @@ int uec_initialize(int index)
 #ifdef CONFIG_UEC_ETH6
 		uec_info = &eth6_uec_info;
 #endif
+	} else if (index == 6) {
+#ifdef CONFIG_UEC_ETH7
+		uec_info = &eth7_uec_info;
+#endif
+	} else if (index == 7) {
+#ifdef CONFIG_UEC_ETH8
+		uec_info = &eth8_uec_info;
+#endif
 	} else {
 		printf("%s: index is illegal.\n", __FUNCTION__);
 		return -EINVAL;
-- 
1.6.0.2