[U-Boot] [PATCH] at91: Add support for MEESC board of esd gmbh

[Jean-Christophe PLAGNIOL-VILLARD]

> +
> +static void meesc_ethercat_hw_init(void)
> +{
> +	/* Configure SMC EBI1_CS0 for EtherCAT */
> +	at91_sys_write(AT91_SMC1_SETUP(0),
> +		AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
> +		AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
> +	at91_sys_write(AT91_SMC1_PULSE(0),
> +		AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
> +		AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
> +	at91_sys_write(AT91_SMC1_CYCLE(0),
> +		AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
> +	/* Configure behavior at external wait signal, byte-select mode, 16 bit
> +	data bus width, none data float wait states and TDF optimization */
> +	at91_sys_write(AT91_SMC1_MODE(0),
> +		AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
> +		AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
> +		AT91_SMC_TDFMODE);
> +
> +	/* Configure RDY/BSY */
> +	at91_set_B_periph(AT91_PIN_PE20, 0);	/* EBI1_NWAIT */
do you really need this
you do not seems to use it anywhere?
> +}
> +
> +#ifdef CONFIG_HAS_DATAFLASH
please keep the file organisation as the other at91sam9
> +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
> +
> +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
> +	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
> +};
> +
> +/* define the area offsets */
> +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
> +	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
> +	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
> +	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
> +};
> +#endif /* CONFIG_HAS_DATAFLASH */
> +
> +int dram_init(void)
> +{
> +	gd->bd->bi_dram[0].start = PHYS_SDRAM;
> +	gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
> +	return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +	int rc = 0;
> +#ifdef CONFIG_MACB
> +	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
> +#endif
> +	return rc;
> +}
> +
> +int checkboard(void)
> +{
> +	char str[32];
> +	char buf[32];
> +
> +	puts("Board: esd CAN-EtherCAT Gateway");
> +	if (getenv_r("serial#", str, sizeof(str)) > 0) {
> +		puts(", serial# ");
> +		puts(str);
> +	}
> +	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
> +	printf("Crystal frequency:\t%8s MHz\n",
> +					strmhz(buf, get_main_clk_rate()));
> +	printf("CPU clock:\t\t%8s MHz\n",
> +					strmhz(buf, get_cpu_clk_rate()));
> +#ifdef CONFIG_SHOW_VERBOSE_CLOCKINFO
> +	printf("Master clock:\t\t%8s MHz\n",
> +					strmhz(buf, get_mck_clk_rate()));
> +	printf("PLL A clock:\t\t%8s MHz\n",
> +					strmhz(buf, get_plla_clk_rate()));
> +	printf("PLL B Reg.:\t\t0x%08X\n",
> +					at91_sys_read(AT91_CKGR_PLLBR));
> +	printf("PLL B clock:\t\t%8s MHz\n",
> +					strmhz(buf, get_pllb_clk_rate()));
> +#endif
> +	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	/* Enable Ctrlc */
> +	console_init_f();
> +
> +	/* Peripheral Clock Enable Register */
> +	at91_sys_write(AT91_PMC_PCER,	1 << AT91SAM9263_ID_PIOA |
> +					1 << AT91SAM9263_ID_PIOB |
> +					1 << AT91SAM9263_ID_PIOCDE);
> +
> +#ifdef MACH_TYPE_MEESC	/* while asm-arm/mach-types.h is not up to date */
you need to send a sync request
> +	/* arch number of MEESC-Board */
> +	gd->bd->bi_arch_number = MACH_TYPE_MEESC;
> +#else
> +	/* arch number of AT91SAM9263EK-Board */
> +	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
please remove
> +#endif
> +	/* adress of boot parameters */
> +	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> +	at91_serial_hw_init();
> +#ifdef CONFIG_CMD_NAND
> +	meesc_nand_hw_init();
> +#endif
> +	meesc_ethercat_hw_init();
> +#ifdef CONFIG_HAS_DATAFLASH
> +	at91_spi0_hw_init(1 << 0);
> +#endif
> +#ifdef CONFIG_MACB
> +	meesc_macb_hw_init();
> +#endif
Best Regards,
J.