[U-Boot] [PATCH] fsl-ddr: Fix the chip-select interleaving issue

[Dave Liu]

commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3
introduced one new bug to chip-select interleaving.

Single DDR controller also can do the chip-select
interleaving if there is dual-rank or qual-rank DIMMs.

Signed-off-by: Dave Liu <daveliu at freescale.com>
---
 cpu/mpc8xxx/ddr/options.c |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index db44291..bfddd6d 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -22,9 +22,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			unsigned int ctrl_num)
 {
 	unsigned int i;
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	const char *p;
-#endif
 
 	/* Chip select options. */
 
@@ -242,6 +240,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 						simple_strtoul(p, NULL, 0);
 		}
 	}
+#endif
 
 	if( (p = getenv("ba_intlv_ctl")) != NULL) {
 		if (strcmp(p, "cs0_cs1") == 0)
@@ -283,7 +282,6 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			break;
 		}
 	}
-#endif
 
 	fsl_ddr_board_options(popts, pdimm, ctrl_num);
 
-- 
1.5.6