[U-Boot] [PATCH] arm_cortexa8: support cache flush to other soc

[Minkyu Kang]

Current code is supported only omap3 soc.
this patch will support s5pc1xx(s5pc100 and s5pc110) soc also.

Signed-off-by: Minkyu Kang <mk7.kang at samsung.com>
---
 cpu/arm_cortexa8/cpu.c |   24 +++++++++++-------------
 1 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 5a5981e..3d430b1 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -35,9 +35,6 @@
 #include <command.h>
 #include <asm/system.h>
 #include <asm/cache.h>
-#ifndef CONFIG_L2_OFF
-#include <asm/arch/sys_proto.h>
-#endif
 
 static void cache_flush(void);
 
@@ -61,17 +58,18 @@ int cleanup_before_linux(void)
 	cache_flush();
 
 #ifndef CONFIG_L2_OFF
-	/* turn off L2 cache */
-	l2_cache_disable();
-	/* invalidate L2 cache also */
-	v7_flush_dcache_all(get_device_type());
-#endif
-	i = 0;
-	/* mem barrier to sync up things */
-	asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
+	if (get_device_type() != 0xC100) {
+		/* turn off L2 cache */
+		l2_cache_disable();
+		/* invalidate L2 cache also */
+		v7_flush_dcache_all(get_device_type());
 
-#ifndef CONFIG_L2_OFF
-	l2_cache_enable();
+		i = 0;
+		/* mem barrier to sync up things */
+		asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
+
+		l2_cache_enable();
+	}
 #endif
 
 	return 0;
-- 
1.5.4.3