[U-Boot] PPC440GX: DDR ECC init time.

[Stefan Roese]

Hi Wouter,

On Friday 04 September 2009 15:06:52 Wouter Eckhardt wrote:
> > 2009.03 is already "old". I suggest you use the 2009.09 release.
> 
> Okay, shouldn't be too much trouble. (You actually meant .08, right? :-)

Of course. :)
 
> > d-cache is the solution.
> 
> That's what I thought as well. Seems that coming up with the solution
> was a bit easier than actually implementing it...
> 
> > Did you flush the caches? You need to be careful here, when changing
> > TLB attributes.
> >
> > Which DDR2 init code are you using btw? A specific custom code with
> > fixed
> > settings? Or the 4xx common SPD code? I suggest you take a look at the
> > common
> > DDR2 code (44x_spd_ddr2.c). ECC handling is done there already with
> > caches enabled. This should give you an idea.
> 
> I didn't flush the cache (seemed a bit pointless since they're not in
> use at that point anyway, right?). I'll give it a whirl. I'll also look
> into the other ECC initialization.

Good.
 
> I actually thought ECC initialization was only done in sdram.c (after a
> quick search for CONFIG_SDRAM_ECC). That probably also answers your next
> question. My SDRAM initialization is the same one as is used for the
> ALPR board and that uses the common code, as far as I know.

Right. After looking at it, the ECC init is done in this common file. But the 
cache handling is missing here. I suggest you try to port this stuff from the 
DDR2 init file I mentioned in my last mail.
 
Cheers,
Stefan

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