[U-Boot] Odd value for I2C_TIMEOUT in fsl_i2c.c

[Peter Tyser]

On Fri, 2009-09-04 at 10:12 -0500, Timur Tabi wrote:
> Wolfgang Denk wrote:
> 
> > Wrong Question. I don't know enough about the I2C protocol. Why is
> > i2c_wait4bus necessary?
> 
> Ok, why is it necessary?

Freescale's I2C core supports multiple masters.  I'd guess that
i2c_wait4bus() is used to ensure the bus is not in use by a different
master before initiating a read or write.  Its polling the MBB status
bit, which is automatically set/cleared when the controller sees a
START/STOP which supports this.

If this is the case, the timeout should be the maximum (or reasonable
maximum) time an I2C transaction could take.

Best,
Peter