[U-Boot] [PATCH v4] ppc/85xx: add boot from NAND/eSDHC/eSPI support

[Kumar Gala]

On Sep 11, 2009, at 1:02 PM, Kumar Gala wrote:

> From: Mingkai Hu <Mingkai.hu at freescale.com>
>
> The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
> implements these three bootup methods in a unified way - all of these
> use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
> which lets us use the SPD to initialize the SDRAM.
>
> For all three bootup methods, the bootup process can be divided into  
> two
> stages: the first stage will initialize the corresponding controller,
> configure the L2SRAM, then copy the second stage image to L2SRAM and
> jump to it. The second stage image is just like the general U-Boot  
> image
> to configure all the hardware and boot up to U-Boot command line.
>
> When boot from NAND, the eLBC controller will first load the first  
> stage
> image to internal 4K RAM buffer because it's also stored on the NAND
> flash. The first stage image, also call 4K NADN loader, will  
> initialize
> the L2SRAM, load the second stage image to L2SRAM and jump to it.  
> The 4K
> NAND loader's code comes from the corresponding nand_spl directory,  
> along
> with the code twisted by CONFIG_NAND_SPL.
>
> When boot from eSDHC/eSPI, there's no such a first stage image because
> the CPU ROM code does the same work. It will initialize the L2SRAM
> according to the config addr/word pairs on the fixed address and
> initialize the eSDHC/eSPI controller, then load the second stage image
> to L2SRAM and jump to it.
>
> The macro CONFIG_SYS_RAMBOOT is used to control the code to produce  
> the
> second stage image for all different bootup methods. It's set in the
> board config file when one of the bootup methods above is selected.
>
> Signed-off-by: Mingkai Hu <Mingkai.hu at freescale.com>
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> ---
> * Merged in changes from other patch into u-boot-nand.lds
> * Fixed up and simplified tlb.c changes
>
> - k

applied to 85xx

- k