[U-Boot] [PATCH 1/7] ppc/p4080: Add p4080 platform immap definitions
Kumar Gala
galak at kernel.crashing.org
Fri Sep 18 22:59:49 CEST 2009
The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform. We reuse the 85xx immap and just add new definitions for
local access and global utils. The global utils is now broken into
global utils, clocking and run control/power management.
The offsets from CCSR for a number of blocks have also changed. We
introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of
platform from the new p4080 platform. We don't use QoirQ as there are
products (like p2020) that are PQ3 based platforms but have the QoirQ
name.
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
include/asm-ppc/fsl_lbc.h | 4 +
include/asm-ppc/immap_85xx.h | 408 +++++++++++++++++++++++++++++++++++++++--
2 files changed, 392 insertions(+), 20 deletions(-)
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index 08d31e1..5723de6 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -317,6 +317,10 @@
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
+#elif defined(CONFIG_FSL_CORENET)
+#define LCRR_CLKDIV_8 0x00000002
+#define LCRR_CLKDIV_16 0x00000004
+#define LCRR_CLKDIV_32 0x00000008
#else
#define LCRR_CLKDIV_4 0x00000002
#define LCRR_CLKDIV_8 0x00000004
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e7d412d..cfcfa5d 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -16,6 +16,150 @@
#include <asm/fsl_i2c.h>
#include <asm/fsl_lbc.h>
+typedef struct ccsr_local {
+ u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */
+ u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */
+ u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */
+#define CCSRAR_C 0x80000000 /* Commit */
+ u8 res1[4];
+ u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */
+ u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */
+ u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */
+ u8 res2[4];
+ u32 bstrh; /* 0x20 - Boot space translation register high */
+ u32 bstrl; /* 0x24 - Boot space translation register Low */
+ u32 bstrar; /* 0x28 - Boot space translation attributes register */
+ u8 res3[0xbd4];
+ u32 lawbarh0; /* 0xc00 - LAW0 base address register high */
+ u32 lawbarl0; /* 0xc04 - LAW0 base address register low */
+ u32 lawar0; /* 0xc08 - LAW0 attributes register */
+ u8 res4[4];
+ u32 lawbarh1; /* 0xc10 - LAW1 base address register high */
+ u32 lawbarl1; /* 0xc14 - LAW1 base address register low */
+ u32 lawar1; /* 0xc18 - LAW1 attributes register */
+ u8 res5[4];
+ u32 lawbarh2; /* 0xc20 - LAW2 base address register high */
+ u32 lawbarl2; /* 0xc24 - LAW2 base address register low */
+ u32 lawar2; /* 0xc28 - LAW2 attributes register */
+ u8 res6[4];
+ u32 lawbarh3; /* 0xc30 - LAW3 base address register high */
+ u32 lawbarl3; /* 0xc34 - LAW3 base address register low */
+ u32 lawar3; /* 0xc38 - LAW3 attributes register */
+ u8 res7[4];
+ u32 lawbarh4; /* 0xc40 - LAW4 base address register high */
+ u32 lawbarl4; /* 0xc44 - LAW4 base address register low */
+ u32 lawar4; /* 0xc48 - LAW4 attributes register */
+ u8 res8[4];
+ u32 lawbarh5; /* 0xc50 - LAW5 base address register high */
+ u32 lawbarl5; /* 0xc54 - LAW5 base address register low */
+ u32 lawar5; /* 0xc58 - LAW5 attributes register */
+ u8 res9[4];
+ u32 lawbarh6; /* 0xc60 - LAW6 base address register high */
+ u32 lawbarl6; /* 0xc64 - LAW6 base address register low */
+ u32 lawar6; /* 0xc68 - LAW6 attributes register */
+ u8 res10[4];
+ u32 lawbarh7; /* 0xc70 - LAW7 base address register high */
+ u32 lawbarl7; /* 0xc74 - LAW7 base address register low */
+ u32 lawar7; /* 0xc78 - LAW7 attributes register */
+ u8 res11[4];
+ u32 lawbarh8; /* 0xc80 - LAW8 base address register high */
+ u32 lawbarl8; /* 0xc84 - LAW8 base address register low */
+ u32 lawar8; /* 0xc88 - LAW8 attributes register */
+ u8 res12[4];
+ u32 lawbarh9; /* 0xc90 - LAW9 base address register high */
+ u32 lawbarl9; /* 0xc94 - LAW9 base address register low */
+ u32 lawar9; /* 0xc98 - LAW9 attributes register */
+ u8 res13[4];
+ u32 lawbarh10; /* 0xca0 - LAW10 base address register high */
+ u32 lawbarl10; /* 0xca4 - LAW10 base address register low */
+ u32 lawar10; /* 0xca8 - LAW10 attributes register */
+ u8 res14[4];
+ u32 lawbarh11; /* 0xcb0 - LAW11 base address register high */
+ u32 lawbarl11; /* 0xcb4 - LAW11 base address register low */
+ u32 lawar11; /* 0xcb8 - LAW11 attributes register */
+ u8 res15[4];
+ u32 lawbarh12; /* 0xcc0 - LAW12 base address register high */
+ u32 lawbarl12; /* 0xcc4 - LAW12 base address register low */
+ u32 lawar12; /* 0xcc8 - LAW12 attributes register */
+ u8 res16[4];
+ u32 lawbarh13; /* 0xcd0 - LAW13 base address register high */
+ u32 lawbarl13; /* 0xcd4 - LAW13 base address register low */
+ u32 lawar13; /* 0xcd8 - LAW13 attributes register */
+ u8 res17[4];
+ u32 lawbarh14; /* 0xce0 - LAW14 base address register high */
+ u32 lawbarl14; /* 0xce4 - LAW14 base address register low */
+ u32 lawar14; /* 0xce8 - LAW14 attributes register */
+ u8 res18[4];
+ u32 lawbarh15; /* 0xcf0 - LAW15 base address register high */
+ u32 lawbarl15; /* 0xcf4 - LAW15 base address register low */
+ u32 lawar15; /* 0xcf8 - LAW15 attributes register */
+ u8 res19[4];
+ u32 lawbarh16; /* 0xd00 - LAW16 base address register high */
+ u32 lawbarl16; /* 0xd04 - LAW16 base address register low */
+ u32 lawar16; /* 0xd08 - LAW16 attributes register */
+ u8 res20[4];
+ u32 lawbarh17; /* 0xd10 - LAW17 base address register high */
+ u32 lawbarl17; /* 0xd14 - LAW17 base address register low */
+ u32 lawar17; /* 0xd18 - LAW17 attributes register */
+ u8 res21[4];
+ u32 lawbarh18; /* 0xd20 - LAW18 base address register high */
+ u32 lawbarl18; /* 0xd24 - LAW18 base address register low */
+ u32 lawar18; /* 0xd28 - LAW18 attributes register */
+ u8 res22[4];
+ u32 lawbarh19; /* 0xd30 - LAW19 base address register high */
+ u32 lawbarl19; /* 0xd34 - LAW19 base address register low */
+ u32 lawar19; /* 0xd38 - LAW19 attributes register */
+ u8 res23[4];
+ u32 lawbarh20; /* 0xd40 - LAW20 base address register high */
+ u32 lawbarl20; /* 0xd44 - LAW20 base address register low */
+ u32 lawar20; /* 0xd48 - LAW20 attributes register */
+ u8 res24[4];
+ u32 lawbarh21; /* 0xd50 - LAW21 base address register high */
+ u32 lawbarl21; /* 0xd54 - LAW21 base address register low */
+ u32 lawar21; /* 0xd58 - LAW21 attributes register */
+ u8 res25[4];
+ u32 lawbarh22; /* 0xd60 - LAW22 base address register high */
+ u32 lawbarl22; /* 0xd64 - LAW22 base address register low */
+ u32 lawar22; /* 0xd68 - LAW22 attributes register */
+ u8 res26[4];
+ u32 lawbarh23; /* 0xd70 - LAW23 base address register high */
+ u32 lawbarl23; /* 0xd74 - LAW23 base address register low */
+ u32 lawar23; /* 0xd78 - LAW23 attributes register */
+ u8 res27[4];
+ u32 lawbarh24; /* 0xd80 - LAW24 base address register high */
+ u32 lawbarl24; /* 0xd84 - LAW24 base address register low */
+ u32 lawar24; /* 0xd88 - LAW24 attributes register */
+ u8 res28[4];
+ u32 lawbarh25; /* 0xd90 - LAW25 base address register high */
+ u32 lawbarl25; /* 0xd94 - LAW25 base address register low */
+ u32 lawar25; /* 0xd98 - LAW25 attributes register */
+ u8 res29[4];
+ u32 lawbarh26; /* 0xda0 - LAW26 base address register high */
+ u32 lawbarl26; /* 0xda4 - LAW26 base address register low */
+ u32 lawar26; /* 0xda8 - LAW26 attributes register */
+ u8 res30[4];
+ u32 lawbarh27; /* 0xdb0 - LAW27 base address register high */
+ u32 lawbarl27; /* 0xdb4 - LAW27 base address register low */
+ u32 lawar27; /* 0xdb8 - LAW27 attributes register */
+ u8 res31[4];
+ u32 lawbarh28; /* 0xdc0 - LAW28 base address register high */
+ u32 lawbarl28; /* 0xdc4 - LAW28 base address register low */
+ u32 lawar28; /* 0xdc8 - LAW28 attributes register */
+ u8 res32[4];
+ u32 lawbarh29; /* 0xdd0 - LAW29 base address register high */
+ u32 lawbarl29; /* 0xdd4 - LAW29 base address register low */
+ u32 lawar29; /* 0xdd8 - LAW29 attributes register */
+ u8 res33[4];
+ u32 lawbarh30; /* 0xde0 - LAW30 base address register high */
+ u32 lawbarl30; /* 0xde4 - LAW30 base address register low */
+ u32 lawar30; /* 0xde8 - LAW30 attributes register */
+ u8 res34[4];
+ u32 lawbarh31; /* 0xdf0 - LAW31 base address register high */
+ u32 lawbarl31; /* 0xdf4 - LAW31 base address register low */
+ u32 lawar31; /* 0xdf8 - LAW31 attributes register */
+ u8 res35[0x204];
+} ccsr_local_t;
+
/*
* Local-Access Registers and ECM Registers(0x0000-0x2000)
*/
@@ -165,7 +309,21 @@ typedef struct ccsr_ddr {
uint debug_2;
uint debug_3;
uint debug_4;
- char res12[240];
+ uint debug_5;
+ uint debug_6;
+ uint debug_7;
+ uint debug_8;
+ uint debug_9;
+ uint debug_10;
+ uint debug_11;
+ uint debug_12;
+ uint debug_13; /* +0xF30 */
+ uint debug_14;
+ uint debug_15;
+ uint debug_16;
+ uint debug_17;
+ uint debug_18; /* +0xF44 */
+ char res12[184];
} ccsr_ddr_t;
/*
@@ -1531,6 +1689,193 @@ typedef struct par_io {
/*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
+#ifdef CONFIG_FSL_CORENET
+typedef struct ccsr_gur {
+ uint porsr1; /* 0xe0000 - POR status register */
+ char res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */
+ uint gpporcr1; /* 0xe0020 - General-purpose POR configuration register */
+ char res2[12];
+ uint gpiocr; /* 0xe0030 - GPIO control register */
+ char res3[12];
+ uint gpoutdr; /* 0xe0040 - General-purpose output data register */
+ char res4[12];
+ uint gpindr; /* 0xe0050 - General-purpose input data register */
+ char res5[12];
+ uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+ char res6[12];
+ uint devdisr; /* 0xe0070 - Device disable control */
+#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
+#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
+#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
+#define FSL_CORENET_DEVDISR_RMU 0x08000000
+#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
+#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
+#define FSL_CORENET_DEVDISR_DMA1 0x00400000
+#define FSL_CORENET_DEVDISR_DMA2 0x00200000
+#define FSL_CORENET_DEVDISR_DDR1 0x00100000
+#define FSL_CORENET_DEVDISR_DDR2 0x00080000
+#define FSL_CORENET_DEVDISR_DBG 0x00010000
+#define FSL_CORENET_DEVDISR_NAL 0x00008000
+#define FSL_CORENET_DEVDISR_ELBC 0x00001000
+#define FSL_CORENET_DEVDISR_USB1 0x00000800
+#define FSL_CORENET_DEVDISR_USB2 0x00000400
+#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
+#define FSL_CORENET_DEVDISR_GPIO 0x00000080
+#define FSL_CORENET_DEVDISR_ESPI 0x00000040
+#define FSL_CORENET_DEVDISR_I2C1 0x00000020
+#define FSL_CORENET_DEVDISR_I2C2 0x00000010
+#define FSL_CORENET_DEVDISR_DUART1 0x00000002
+#define FSL_CORENET_DEVDISR_DUART2 0x00000001
+ char res7[12];
+ uint powmgtcsr; /* 0xe0080 - Power management status and control register */
+ char res8[12];
+ uint coredisru; /* 0xe0090 - uppper portion for support of 64 cores */
+ uint coredisrl; /* 0xe0094 - lower portion for support of 64 cores */
+ char res9[8];
+ uint pvr; /* 0xe00a0 - Processor version register */
+ uint svr; /* 0xe00a4 - System version register */
+ char res10[8];
+ uint rstcr; /* 0xe00b0 - Reset control register */
+ uint rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */
+ char res11[8];
+ uint rstrqmr1; /* 0xe00c0 - Reset request mask register */
+ char res12[4]; /* Reserved: RSTRQMR2 */
+ uint rstrqsr1; /* 0xe00c8 - Reset request status register */
+ char res13[4]; /* Reserved: RSTRQSR2 */
+ char res14[4]; /* Reserved: RSTRQWDTMRU */
+ uint rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */
+ char res15[4]; /* Reserved: RSTRQWDTSRU */
+ uint rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */
+ char res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */
+ uint brrl; /* 0xe00e4 Boot release register */
+ char res17[24];
+ uint rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */
+#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
+#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15
+#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
+ char res18[192]; /* Reserved: RCWSRn (max total of 64)*/
+ uint scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */
+ char res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/
+ uint scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */
+ char res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/
+ uint scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */
+ char res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/
+ uint pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/
+ uint pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/
+ uint pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/
+ uint pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/
+ uint rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/
+ uint rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/
+ uint rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/
+ uint rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/
+ uint usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/
+ uint usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/
+ uint usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/
+ uint usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/
+ uint sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/
+ uint sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/
+ uint sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/
+ uint sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/
+ uint rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/
+ uint rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/
+ uint rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/
+ char res22[52]; /* Reserved: for future LIODN register expansion */
+ uint dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/
+ uint dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/
+ uint dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/
+ uint dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/
+ char res23[48]; /* Reserved: for future LIODN register expansion */
+ char res24[64]; /* Reserved */
+ uint pblsr; /* 0xe0600 Preboot loader status register*/
+ uint pamubypenr; /* 0xe0604 PAMU bypass enable register*/
+ uint dmacr1; /* 0xe0608 DMA control register*/
+ char res25[4]; /* Reserved: DMACR2 (max total of 2)*/
+ uint gensr1; /* 0xe0610 General status register*/
+ char res26[12]; /* Reserved: GENSRn (max total of 4)*/
+ uint gencr1; /* 0xe0620 General control register*/
+ char res27[12]; /* Reserved: GENCRn (max total of 4)*/
+ char res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */
+ uint cgensrl; /* 0xe0634 Core general status register*/
+ char res29[8]; /* Reserved */
+ char res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */
+ uint cgencrl; /* 0xe0634 Core general control register*/
+ char res31[184]; /* Reserved 0xe0648 - 0xe06fc */
+ uint sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/
+ char res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */
+} ccsr_gur_t;
+
+typedef struct ccsr_clk {
+ u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */
+ u8 res1[0x1c];
+ u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */
+ u8 res2[0x1c];
+ u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */
+ u8 res3[0x1c];
+ u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */
+ u8 res4[0x1c];
+ u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */
+ u8 res5[0x1c];
+ u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */
+ u8 res6[0x1c];
+ u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */
+ u8 res7[0x1c];
+ u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */
+ u8 res8[0x71c];
+ u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */
+ u8 res10[0x1c];
+ u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */
+ u8 res11[0x1c];
+ u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */
+ u8 res12[0x1c];
+ u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */
+ u8 res13[0x39c];
+ u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */
+ u8 res14[0x1c];
+ u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */
+ u8 res15[0x3dc];
+} ccsr_clk_t;
+
+typedef struct ccsr_rcpm {
+ u8 res1[4]; /* 0xe2000 - Reserved */
+ u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */
+ u8 res2[4]; /* 0xe2008 - Reserved */
+ u32 cdozcrl; /* 0xe200c - Core Doze Control Register */
+ u8 res3[4]; /* 0xe2010 - Reserved */
+ u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */
+ u8 res4[4]; /* 0xe2018 - Reserved */
+ u32 cnapcrl; /* 0xe201c - Core Nap Control Register */
+ u8 res5[4]; /* 0xe2020 - Reserved */
+ u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */
+ u8 res6[4]; /* 0xe2028 - Reserved */
+ u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */
+ u8 res7[4]; /* 0xe2030 - Reserved */
+ u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */
+ u8 res8[8]; /* Reserved */
+ u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */
+ u8 res9[12]; /* Reserved */
+ u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */
+ u8 res10[12]; /* Reserved */
+ u8 res11[4]; /* Reserved */
+ u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */
+ u8 res12[4]; /* Reserved */
+ u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */
+ u8 res13[4]; /* Reserved */
+ u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */
+ u8 res14[4]; /* Reserved */
+ u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */
+ u8 res15[4]; /* Reserved */
+ u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */
+ u8 res16[4]; /* Reserved */
+ u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */
+ u8 res17[4]; /* Reserved */
+ u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */
+ u8 res18[0xf68];
+} ccsr_rcpm_t;
+
+#else
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
#ifdef CONFIG_MPC8536
@@ -1645,42 +1990,65 @@ typedef struct ccsr_gur {
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
+#endif
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
+#ifdef CONFIG_FSL_CORENET
+#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET (0x0000)
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x8000)
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x9000)
+#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET (0xE1000)
+#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET (0xE2000)
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x100000)
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x110000)
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x114000)
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x124000)
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0x130000)
+#define CONFIG_SYS_MPC85xx_QMAN_OFFSET (0x318000)
+#define CONFIG_SYS_MPC85xx_BMAN_OFFSET (0x31a000)
+#else
+#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000)
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000)
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000)
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000)
+#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
+#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000)
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000)
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000)
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000)
+#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000)
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000)
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000)
+#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100)
+#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000)
+#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000)
+#endif
+
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000)
+#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
+
+#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET)
+#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
-#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
+#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
-#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000)
#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000)
#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000)
#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000)
#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000)
-#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000)
+#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000)
#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
-#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000)
#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000)
#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000)
#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000)
#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000)
#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000)
#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100)
#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
#define CONFIG_SYS_MPC85xx_USB_ADDR \
--
1.6.0.6
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