[U-Boot] [PATCH v3 3/7] ppc/p4080: CoreNet platfrom style CCSRBAR setting

[Kumar Gala]

On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.

Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood at freescale.com>
---
* Updated based on LAWs being an array

 cpu/mpc85xx/cpu_init_early.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c
index 7886f86..5cd0815 100644
--- a/cpu/mpc85xx/cpu_init_early.c
+++ b/cpu/mpc85xx/cpu_init_early.c
@@ -54,6 +54,9 @@ void cpu_init_early_f(void)
 		u32 temp;
 		volatile u32 *ccsr_virt =
 			(volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+#ifdef CONFIG_FSL_CORENET
+		volatile ccsr_local_t *ccm;
+#endif
 
 		mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
 		/* mas1 is the same as above */
@@ -64,9 +67,35 @@ void cpu_init_early_f(void)
 
 		write_tlb(mas0, mas1, mas2, mas3, mas7);
 
+#ifdef CONFIG_FSL_CORENET
+		/*
+		 * We can't call set_law() because we haven't moved
+		 * CCSR yet.
+		 */
+		ccm = (void *)ccsr_virt;
+
+		out_be32(&ccm->law[0].lawbarh,
+			(u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
+		out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
+		out_be32(&ccm->law[0].lawar,
+			LAWAR_EN | (0x1e << 20) | LAW_SIZE_4K);
+
+		in_be32((u32 *)(ccsr_virt + 0));
+		in_be32((u32 *)(ccsr_virt + 1));
+		isync();
+
+		ccm = (void *)CONFIG_SYS_CCSRBAR;
+		/* Now use the temporary LAW to move CCSR */
+		out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
+		out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
+		out_be32(&ccm->ccsrar, CCSRAR_C);
+		temp = in_be32(&ccm->ccsrar);
+		disable_law(0);
+#else
 		temp = in_be32(ccsr_virt);
 		out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
 		temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
+#endif
 	}
 #endif
 
-- 
1.6.0.6