[U-Boot] [PATCH 0/6] sbc8548 update; remaining bits for 85xx tree.

[Paul Gortmaker]

This is the remaining bits that weren't merged to 85xx, with the
the requested fixes of course.  Those being:

sbc8548: correct local bus SDRAM size from 64M to 128M
	-now uses I/O accesors on BR4/OR4

sbc8548: update PCI/PCI-e support code
	-redone to make use of the code de-duplification effort.

sbc8548: allow enabling PCI via a make config option
	-uses the "-t" to de-clutter the toplevel Makefile

New patches are as follows:
 fsl_pci: create a SET_STD_PCI_INFO() helper wrapper
	-I believe this was meant to be created, but wasn't.

sbc8548: use I/O accessors
	-uses the I/O accessors through the whole board file.

sbc8548: remove eTSEC3/4 voltage hack
	-noticed this while doing above; sbc doesn't need it.

Board still seems happy; I only noticed one cosmetic thing, that
the new fsl_pci_init_port() prints "PCIE" always; even when the
port is PCI and not PCI-e (see below).

Thanks,
Paul.

U-Boot 2009.08-06732-g70c5c3d (Sep 20 2009 - 20:11:42)                          
                                                                                
CPU:   8548E, Version: 2.0, (0x80390020)                                        
Core:  E500, Version: 2.0, (0x80210020)                                         
Clock Configuration:                                                            
       CPU0:990  MHz,                                                           
       CCB:396  MHz,                                                            
       DDR:198  MHz (396 MT/s data rate), LBC:99   MHz                          
L1:    D-cache 32 kB enabled                                                    
       I-cache 32 kB enabled                                                    
Board: Wind River SBC8548 Rev. 0x2                                              
I2C:   ready                                                                    
DRAM:  Initializing                                                             
    SDRAM: 128 MB                                                               
    DDR: 256 MB                                                                 
FLASH: 72 MB                                                                    
L2:    512 KB enabled                                                           
    PCI host: 64 bit, 66 MHz, sync, arbiter                                     
               Scanning PCI bus 00                                              
        00  01  8086  1026  0200  00                                            
    PCIE1 on bus 00 - 00                                                        
                                                                                
    PCIE at base address e000a000                                               
               Scanning PCI bus 02                                              
        02  00  1148  9e00  0200  00                                            
    PCIE1 on bus 01 - 02                                                        
                                                                                
In:    serial                                                                   
Out:   serial                                                                   
Err:   serial                                                                   
Net:   eTSEC0, eTSEC1                                                           
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