[U-Boot] [PATCH] ppc/85xx: Fix enabling of L2 cache

[Kumar Gala]

We need to flash invalidate the locks in addition to the cache
before we enable.

Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
 cpu/mpc85xx/cpu_init.c |    4 ++--
 cpu/mpc85xx/release.S  |    3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 428b461..726182f 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -348,8 +348,8 @@ int cpu_init_r(void)
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 
 	/* invalidate the L2 cache */
-	mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
-	while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
+	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
+	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 		;
 
 	/* enable the cache */
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 074b056..ecbd0d5 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -102,7 +102,8 @@ __secondary_start_page:
 #ifdef CONFIG_BACKSIDE_L2_CACHE
 	/* Enable/invalidate the L2 cache */
 	msync
-	lis	r3,L2CSR0_L2FI at h
+	lis	r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
+	ori	r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
 	mtspr	SPRN_L2CSR0,r3
 1:
 	mfspr	r3,SPRN_L2CSR0
-- 
1.6.0.6