[U-Boot] [PATCH v4 6/7] ppc/p4080: Handle timebase enabling and frequency reporting

[Wolfgang Denk]

Dear Kumar Gala,

In message <1253380099-27864-6-git-send-email-galak at kernel.crashing.org> you wrote:
> On CoreNet style platforms the timebase frequency is the bus frequency
> defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
> the core not longer controls the enabling of the timebase.  We now need
> to enable the boot core's timebase via CCSR register writes.
> 
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
...
> diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
> index a6d1e99..428b461 100644
> --- a/cpu/mpc85xx/cpu_init.c
> +++ b/cpu/mpc85xx/cpu_init.c
> @@ -229,6 +229,18 @@ void cpu_init_f (void)
>  #if defined(CONFIG_FSL_DMA)
>  	dma_init();
>  #endif
> +#ifdef CONFIG_FSL_CORENET
> +	{
> +		volatile ccsr_rcpm_t *rcpm =
> +			(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
> +		volatile ccsr_pic_t *pic =
> +			(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
> +		u32 whoami = in_be32(&pic->whoami);
> +
> +		/* Enable the timebase register for this core */
> +		out_be32(&rcpm->ctbenrl, (1 << whoami));
> +	}
> +#endif

Please do not add variable declarations right in the middle of a
function.


Best regards,

Wolfgang Denk

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panic: kernel trap (ignored)