[U-Boot] [PATCH] Fixed ordering of MDDRC config registers to unbreak mpc5121ads patch

[Martha M Stan]

3rd time's a charm -- Wolfgang had also changed the Elpida patch one so I fixed the reg ordering in it too.

Signed-off-by: Martha M Stan <mmarx at silicontkx.com>
---
 board/freescale/mpc5121ads/mpc5121ads.c |    2 +-
 cpu/mpc512x/fixed_sdram.c               |   29 ++++++++++++++++++++---------
 2 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 13bd73c..a5be586 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -170,10 +170,10 @@ phys_size_t initdram(int board_type)
 	 * to the Default Micron ones for all but the earliest Rev 4 boards
 	 */
 	u32 elpida_mddrc_config[4] = {
+		CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
 		CONFIG_SYS_MDDRC_TIME_CFG0,
 		CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
 		CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
-		CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
 	};
 
 	u32 elpida_init_sequence[] = {
diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c
index 673d61e..1f6295f 100644
--- a/cpu/mpc512x/fixed_sdram.c
+++ b/cpu/mpc512x/fixed_sdram.c
@@ -26,13 +26,13 @@
 #include <asm/mpc512x.h>
 
 /*
- * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers
+ * MDDRC Config Runtime Settings in MEMORY order of the 4 MDDRC cfg registers
  */
 u32 default_mddrc_config[4] = {
+	CONFIG_SYS_MDDRC_SYS_CFG,	/* sys_config	*/
 	CONFIG_SYS_MDDRC_TIME_CFG0,	/* time_config0 */
 	CONFIG_SYS_MDDRC_TIME_CFG1,	/* time_config1 */
-	CONFIG_SYS_MDDRC_TIME_CFG2,	/* time_config2 */
-	CONFIG_SYS_MDDRC_SYS_CFG,	/* sys_config	*/
+	CONFIG_SYS_MDDRC_TIME_CFG2	/* time_config2 */
 };
 
 u32 default_init_seq[] = {
@@ -79,6 +79,12 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz)
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
+	struct ddr512x_4regs {
+		u32 ddr_sys_config;
+		u32 ddr_time_config0;
+		u32 ddr_time_config1;
+		u32 ddr_time_config2;
+	} *mddrc_4regs;
 	u32 i;
 
 	/* take default settings and init sequence if necessary */
@@ -130,18 +136,23 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz)
 	 *  put MDDRC in CMD mode and
 	 *  set the max time between refreshes to 0 during init process
 	 */
-	out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK);
-	out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK);
-	out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]);
-	out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]);
+
+	/* using mddrc's first 4 regs only */
+	mddrc_4regs = (struct ddr512x_4regs *)mddrc_config; 
+	out_be32(&im->mddrc.ddr_sys_config, mddrc_4regs->ddr_sys_config
+						| MDDRC_SYS_CFG_CMD_MASK);
+	out_be32(&im->mddrc.ddr_time_config0, mddrc_4regs->ddr_time_config0
+						& MDDRC_REFRESH_ZERO_MASK);
+	out_be32(&im->mddrc.ddr_time_config1, mddrc_4regs->ddr_time_config1);
+	out_be32(&im->mddrc.ddr_time_config2, mddrc_4regs->ddr_time_config2);
 
 	/* Initialize DDR with either default or supplied init sequence */
 	for (i = 0; i < seq_sz; i++)
 		out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
 
 	/* Start MDDRC */
-	out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]);
-	out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]);
+	out_be32(&im->mddrc.ddr_time_config0, mddrc_4regs->ddr_time_config0);
+	out_be32(&im->mddrc.ddr_sys_config, mddrc_4regs->ddr_sys_config);
 
 	return msize;
 }
-- 
1.5.2.4